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高性能并行乘法器半定制设计方法研究

发布时间:2018-02-13 17:56

  本文关键词: 乘法器 标准单元库扩展 改进的Booth编码算法 Wallace树 逻辑功效 出处:《浙江大学》2012年硕士论文 论文类型:学位论文


【摘要】:乘法器是微处理器中的重要部件,它的设计与实现直接影响着整个数字系统的性能,因此高性能乘法器的设计仍然被关注。另一方面,激烈的市场竞争加速了产品的上市进程,从而要求设计者尽量缩短设计时间。为了兼顾乘法器的性能和设计时间,通常使用基于标准单元库的半定制设计方法。但是传统的半定制设计方法受限于库中标准单元有限的驱动能力,无法实现最短路径延时。为此,本文提出了基于标准单元库扩展的乘法器设计方法,消除了传统方法的不足。 本文设计并实现17 bit×17 bit带符号数字乘法器。为了提高乘法器的性能,采用改进的Booth编码算法,Wallace树形结构,以及基于标准单元库扩展的设计方法。该方法使用逻辑功效模型分析乘法器的关键路径,通过构造驱动能力更为完备的单元以实现关键路径中每一级门功效相等,从而得到最短路径延时。将TSMC 90nm标准单元库扩展得到扩展单元库,使用两个单元库分别版图实现数字乘法器,基于扩展单元库实现的乘法器速度提升10.87%。实验结果表明,基于标准单元库扩展的半定制设计方法可以有效提升电路的性能,这种方法尤其适用于电路负载过大的情况。
[Abstract]:Multiplier is an important component in microprocessor, its design and implementation directly affect the performance of the whole digital system, so the design of high performance multiplier is still concerned. On the other hand, fierce market competition accelerates the process of product marketing. The designer is required to shorten the design time as much as possible. The semi-custom design method based on standard cell library is usually used. However, the traditional semi-custom design method is limited by the limited drive ability of the standard unit in the library, so it can not achieve the shortest path delay. In this paper, a multiplier design method based on standard cell library extension is proposed, which eliminates the shortcomings of traditional methods. In this paper, a 17 bit 脳 17 bit signed digital multiplier is designed and implemented. In order to improve the performance of the multiplier, an improved Booth coding algorithm is proposed. The method uses logical efficacy model to analyze the critical path of multiplier, and constructs a more complete drive unit to achieve the equal efficiency of every step gate in the critical path. The TSMC 90nm standard cell library is extended to obtain the extended cell library, and the digital multiplier is implemented by using the two cell libraries respectively. The speed of the multiplier based on the extended cell library is increased by 10.87. the experimental results show that, The semi-custom design method based on the expansion of standard cell library can effectively improve the performance of the circuit. This method is especially suitable for the case of excessive circuit load.
【学位授予单位】:浙江大学
【学位级别】:硕士
【学位授予年份】:2012
【分类号】:TP332.22

【引证文献】

相关硕士学位论文 前2条

1 李碧琛;基于可扩展标准单元的电路设计方法研究[D];浙江大学;2013年

2 李辉华;PowerPC处理器整数运算单元的设计与实现[D];西安电子科技大学;2013年



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