双控制器磁盘阵列中PCI-e同步通道的优化技术研究

发布时间：2018-02-14 15:15

本文关键词： 磁盘阵列双控制服务器同步通道　出处：《华中科技大学》2012年硕士论文　论文类型：学位论文

【摘要】：为了提高数据存储的可靠性，双控制器磁盘阵列使用越来越广泛。在双控盘陈列中，控制器间的数据同步是决定其性能和可靠性的关键因素。在自主研发的双控中，采用PCI-e作为同步通道，可以在传输速率上满足性能要求。但其本身也存在许多的问题。一方面，PCI-e板卡使用RDMA传输方式，在传输小块数据时性能会急剧下降。另一方面，传统的PCI-e通信设计是针对于多点（节点数2）的情况，而在双控制服务器磁盘阵列中的数据同步是一种点到点的传输模式。因此，一方面需要解决传输小块数据的问题。另一方面需要简化现有的PCI-e传输层次。在传输方式中，SISCI层中的共享内存是直接由CPU来掌管的传输方式，在存储小块数据时不会有性能下降的问题。在改进之后的传输模式中，选择将RDMA和共享内存的传输方式结合起来。在发送方发送结束后，使用中断的方式来通知接收方已经发送完毕，解放CPU去完成其他的工作。在传输的开始和结束时，分别有错误检测模块来进行错误检测，并发送错误报告。整个接口应用在SISCI层之上，避开了supersocket层上繁琐的管理步骤，简化了PCI-e的层次结构。在对PCI-e做出改进之后，使用共享内存的方式解决了其在传输小块数据时的速率下降问题，同时保留了RDMA在传输大块数据的传输高效性。改进之后在传输小块数据时，传输速率提升4-6倍。改进之后的传输通道一方面作为程序的接口，可以被Cache同步模块直接调用，，可以根据用户的需求，选择合适的数据块大小进行传输。同时，可以通过包括错误检测，中断提示来保证数据传输的完整性。
[Abstract]:In order to improve the reliability of data storage, dual-controller disk array is more and more widely used. In dual-controller display, data synchronization between controllers is the key factor to determine its performance and reliability. Using PCI-e as the synchronization channel can meet the performance requirements in the transmission rate. However, there are many problems in itself. On the one hand, the performance of PCI-e card with RDMA transmission mode will drop sharply when transmitting small data, on the other hand, The traditional design of PCI-e communication is aimed at the situation of multi-point (2 points), but the data synchronization in the dual-control server disk array is a point-to-point transmission mode. On the one hand, we need to solve the problem of transferring small pieces of data, on the other hand, we need to simplify the existing PCI-e transport hierarchy. The shared memory in the SISCI layer in the transport mode is directly managed by CPU, and there is no problem of performance degradation when storing small pieces of data. Select a combination of RDMA and shared memory transport. After the sender sends, use an interrupt to notify the receiver that the sending has finished, liberate the CPU to do other work. At the beginning and end of the transmission, The whole interface is applied on the SISCI layer, avoiding the tedious management steps on the supersocket layer, and simplifies the hierarchy of PCI-e. After the improvement of PCI-e, it solves the problem of rate decreasing when transferring small pieces of data by using shared memory, while keeping the efficiency of transferring large pieces of data in RDMA. The transmission rate is increased 4-6 times. The improved transmission channel can be called directly by the Cache synchronization module, on the one hand, as the interface of the program. At the same time, it can select the appropriate data block size for transmission according to the needs of the user. At the same time, The integrity of data transmission can be ensured by including error detection and interrupt prompts.
【学位授予单位】：华中科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333.35

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