位线漏电流对高速SRAM设计的影响与对应消除技术

发布时间：2018-02-22 01:31

本文关键词： SRAM 位线漏电流漏电流补偿与降低技术位线自截断技术位线取反放大技术　出处：《安徽大学》2012年硕士论文　论文类型：学位论文

【摘要】：随着SRAM在PC,网络,移动通信等需要快速存取与传输数据的应用领域的不断拓展,人们对高速SRAM的需求也会随之不断增长。然而随着半导体工艺的不断进步,器件的漏电流也呈现出越来越大的增长趋势。漏电流的增大会给高速SRAM的设计带来许多新的问题与挑战,其中‘个重大的问题就是存在于SRAM位线上的过大漏电流会造成SRAM的性能出现严重下降甚至会直接导致SRAM读失效的发生。针对这一问题,本文深入研究了位线漏电流对高速SRAM设计的影响并提出各种消除该影响的技术与方法。本文的主要研究工作如下： 1,论文首先分析了‘款传统的位线漏电流补偿电路,通过建立合适的电路模型对该种漏电流的补偿工作机理进行了分析,得出的结论认为这种预先检测漏电流然后全部补偿的方法有可能导致SRAM的性能出观下降； 2,基于1所得出的结论,本文设计了两款新的漏电流补偿电路,这两款补偿电路均放弃了之前的预先检测后补偿的步骤,而是直接检测两根位线的电位变化率,并在电路实现过程中中根据被检测信号的电位变化率的不同自动形成正反馈回路,从而让两根位线中放电较慢的一根位线放电更慢而让放电较快的一根位线放电更快,从而消除位线上存在的较大漏电流对SRAM的不利影响； 3,本论文然后结合2中所提出的一款漏电流补偿电路进一步提出一种新型电流型SA的电路设计,以实现在存在较大漏电流的大背景下提高SRAM性能的目的; 4,针对漏电流进‘步增大,特别是当最坏情况‘下位线上所积累的漏电流已经超过SRAM的工作电流的情况,由于传统的一些方法与技术在这一新的范畴内将趋于失效,于是本论文试图对这一情况进行一些探索性地研究,并提出可以采用位线自截断技术来消除过大漏电流对SRAM的不利影响; 5,针对4中所提出的位线自截断技术存在的性能上限问题,本论文通过结合分级位线技术,位线白截断技术以及电荷分享技术等更进一步地提出一种位线取反放大技术,该技术可以在存在较大位线漏电流的情况下实现进一步提升SRAM性能的目的。
[Abstract]:With the development of SRAM applications in PCS, network, mobile communication and so on, the demand for high-speed SRAM will increase. However, with the progress of semiconductor technology, The leakage current of the device also shows an increasing trend. The increase of leakage current will bring many new problems and challenges to the design of high-speed SRAM. One of the major problems is that the excessive leakage current on the SRAM bit line will cause a serious decline in the performance of the SRAM and even lead directly to the SRAM reading failure. In this paper, the influence of bit line leakage current on the design of high speed SRAM is deeply studied, and various techniques and methods to eliminate this effect are put forward. The main work of this paper is as follows:. 1. Firstly, the paper analyzes the traditional bit line leakage current compensation circuit, and analyzes the compensation mechanism of the leakage current by establishing an appropriate circuit model. The conclusion is that this method of detecting leakage current in advance and compensating it completely may lead to the degradation of SRAM performance. 2. Based on the conclusion of 1, two new leakage current compensation circuits are designed in this paper. These two compensation circuits abandon the previous steps of pre-detection and compensation, but directly detect the potential change rate of two bit lines. In the realization of the circuit, the positive feedback loop is automatically formed according to the change rate of the potential of the detected signal, so that the slower one bit line in the two bit lines and the faster one bit line discharge faster. In order to eliminate the negative effect of the large leakage current on the bit line on SRAM; 3. In this paper, a novel current mode SA circuit is designed based on a leakage current compensation circuit proposed in 2, so as to improve the performance of SRAM under the background of large leakage current. 4. In view of the stepwise increase of leakage current, especially when the accumulated leakage current on the worst-case line has exceeded the operating current of SRAM, some traditional methods and techniques will tend to fail in this new category. Therefore, this paper attempts to do some exploratory research on this situation, and proposes that the bit-line self-truncation technique can be used to eliminate the adverse effects of excessive leakage current on SRAM. 5. Aiming at the performance upper limit problem of bit line self-truncation technology proposed in 4, this paper proposes a bit line reverse amplification technique by combining hierarchical bit line technology, bit line white truncation technique and charge sharing technology. This technique can further improve the performance of SRAM in the presence of large bit line leakage current.
【学位授予单位】：安徽大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333

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