高速低功耗静态随机存储器设计与验证

发布时间：2018-02-24 03:08

本文关键词： 静态随机存储器低功耗稳定性高速　出处：《北京交通大学》2013年硕士论文　论文类型：学位论文

【摘要】：现代集成电路(IC)设计中硅片面积的大部分是用于存储相关数据值和程序指令。随着半导体业的飞速发展,对存储器的需求突飞猛涨。而静态随机存储器(SRAM)以其无需刷新、使用方便以及速度较快等优势占据关键地位。进入纳米工艺技术水平后,对SRAM性能的要求日益严格,尤其是其稳定性、功耗和速度等方面。尤其是在40nm CMOS工艺节点以后,电路设计受工艺的影响因素增大,综合性的高性能成为发展趋势。本文设计的出发点是,设计一款高稳定性低功耗的高速芯片。确定需求后,在具体设计时,首先需要设计一款低功耗的SRAM芯片；其次,考虑电路设计复杂度的前提下,改进电路设计,优化SRAM芯片的读取时间,提升SRAM芯片的读取速度。实际采取的设计方案是,基于40nm低功耗CMOS工艺技术,综合考虑芯片的稳定性和速度,对存储单元阵列部分进行设计以及外围电路的合理设计,实现低功耗的需求。其次,在低功耗电路的基础上对该电路进行改进优化,减小SRAM芯片的读取时间,使得设计的SRAM芯片的速度能够在众多低功耗的芯片中有较大的竞争力。该部分主要采取的可行性方法是针对外围电路进行分析改进,优化SRAM芯片的读取速度。本文采用目前稳定的40nm低功耗CMOS工艺技术,通过设计电路最终实现高稳定性低功耗的高速静态存储器SRAM的设计。经过测试验证,采用40nm低功耗工艺技术,设计的静态存储器的功耗能够与当前低功耗水平持平,同时在速度方面,取得了较大的提升。该设计方案最终经过流片测试验证成功。
[Abstract]:Most of the silicon chip area in modern IC) design is used to store related data values and program instructions. With the rapid development of semiconductor industry, the demand for memory has skyrocketed, while the static random access memory (SRAM) does not need to be refreshed. The advantages of easy to use and fast speed occupy a key position. After entering the level of nanotechnology, the performance of SRAM becomes more and more strict, especially in terms of its stability, power consumption and speed, especially after the 40nm CMOS process node. The design of the circuit is influenced by the process, and the comprehensive high performance becomes the development trend. The starting point of this paper is to design a high speed chip with high stability and low power consumption. After determining the requirements, we need to design a low power SRAM chip first. Secondly, considering the complexity of the circuit design, Improve the circuit design, optimize the read time of SRAM chip, improve the read speed of SRAM chip. The actual design scheme is based on 40nm low power CMOS technology, considering the stability and speed of the chip, The memory cell array part is designed and the peripheral circuit is reasonably designed to realize the demand of low power consumption. Secondly, the circuit is improved and optimized on the basis of low power consumption circuit to reduce the reading time of SRAM chip. The speed of the designed SRAM chip can be competitive in many low-power chips. The feasibility method adopted in this part is to improve the peripheral circuit and optimize the reading speed of the SRAM chip. In this paper, the stable 40nm low power CMOS technology is adopted, and the design of high stability and low power high speed static memory SRAM is realized through the design of the circuit. After testing, the 40nm low power technology is adopted. The power consumption of the designed static memory can be equal to the current low power level, and the speed has been greatly improved. Finally, the design was verified successfully by flow sheet test.
【学位授予单位】：北京交通大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333

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