VMM验证平台中ISO14443通讯接口的参考模型建立

发布时间：2018-02-26 09:21

本文关键词： 验证 VMM SystemVerilog 参考模型　出处：《西安电子科技大学》2013年硕士论文　论文类型：学位论文

【摘要】：随着数字集成电路规模越来越大,设计越来越复杂,验证的难度也随之增加,设计新加一项功能,验证增加不止一条测试案例,实际项目中验证所占时间更是高达整个项目研发周期的70%,搭建高效的验证平台,开发优秀的验证环境,成了当前集成电路设计工作的重要任务。目前双界面卡的应用在国内乃至国际迅猛发展,已经证明了双界面卡应用的美好前景。本文就双界面卡中符合ISO/IEC14443协议的非接触射频通讯接口模块验证提出的一种更高效的验证方法,即在传统的基于VMM采用随机约束激励的验证平台中,加入高抽象语言SystemVerilog搭建的参考模型,参考模型提供的黄金响应使得对DUT功能正确性的判定变得更加简单高效,参考模型的加入也使得注入错误的验证得以轻松实现,在验证平台中加入参考模型大幅提高了验证效率,同时也提高了验证平台的可重用性能、可移植性,缩短了芯片研发周期。本论文首先介绍阐述了VMM验证方法学,之后介绍ISO/IEC14443通讯协议以及DUT的RTL设计规范,随后将传统验证平台与参考模型验证平台做出比较说明。本论文中,重点工作是设计编写射频通讯接口的参考模型,论文中重点介绍说明了参考模型设计方法以及代码结构,参考模型设计编写完成后,嵌入到传统的验证环境中,进行前端RTL仿真,仿真结果表明,在传统验证环境中加入参考模型能提高验证的覆盖率。
[Abstract]:As the scale of the digital integrated circuit becomes more and more complex , the design becomes more and more complex , the difficulty of verification is increased , the design of a new function is added , the verification is increased more than one test case , the verification in the actual project is more than 70 % of the whole project development cycle , a high - efficiency verification platform is built , and an excellent verification environment is developed , and the important task of the current integrated circuit design work is developed . At present , the application of the dual - interface card in the domestic and even the international swift development has proved the good prospect of the dual - interface card application . In this paper , a more efficient verification method is proposed for the verification of the non - contact radio frequency communication interface module conforming to the ISO / IEC 14443 protocol in the dual - interface card . In the verification platform based on the random constraint excitation in the dual - interface card , the reference model provided by the reference model makes the judgment of the correctness of the function of the DUT more simple and efficient , and the reference model adds a reference model to greatly improve the verification efficiency , and simultaneously improves the reusability and the portability of the verification platform , and shortens the development cycle of the chip . This paper first introduces the methodology of VMM verification , then introduces the ISO / IEC 14443 communication protocol and the RTL design specification of the DUT , and then compares the traditional verification platform with the reference model verification platform . In this paper , the emphasis work is to design the reference model of the radio frequency communication interface . In this paper , the design method of the reference model and the code structure are described in this paper . After the design of the reference model is completed , the design of the reference model is embedded in the traditional verification environment , and the RTL simulation is carried out . The simulation results show that the reference model can be added to the traditional verification environment to improve the coverage of verification .

【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP334.7

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