基于APB总线的同步串行接口IP设计与验证

发布时间：2018-02-27 21:31

本文关键词： SOC IP核 APB总线同步串行接口 Verilog HDL　出处：《西安电子科技大学》2013年硕士论文　论文类型：学位论文

【摘要】：近年来SOC设计产业飞速发展，其设计复杂度也日趋增加。SOC设计领域面临这两大挑战，一是以设计重用为目的的IP复用技术，二是以可复用IP核为基础的IP互连技术。因此对IP复用技术的研究在SOC设计行业内具有重要意义。同步串行接口技术是一种高速全双工同步串行通信总线，具有线路简单，节约功耗等优点，广泛应用于各类SOC设计中。论文设计的通用同步串行接口IP核，支持SPI、SSP和Microwire三种串行协议，可配置为主从模式与外部串行设备进行数据通信。这种灵活的可配置性和通用性符合SOC设计技术发展方向，具有很高的实用价值。随着IP复用技术的推广，片上总线技术也得到了迅速发展。本文分析对比了Wishbo ne、CoreConnect、Avalon、AMBA总线的技术特点。其中，AMBA总线配置简单、使用灵活、功能强大，并且拥有众多第三方支持，，特别是AMBA总线架构中的APB高级外设总线，具有技术简单、功耗低、实用性强的优点，应用前景广阔。根据自顶向下的设计思路，论述了基于APB总线的同步串行接口IP核的设计方法。首先分析设计目标和需求，定义了模块外部输入输出接口。然后根据设计功能划分子模块，给出完整IP核模块结构框图，以及详细端口和寄存器说明。接着详细讨论了IP核各个子模块的具体功能和设计思路。根据验证计划，使用Modelsim对SSI接口IP核的RTL代码进行了功能仿真。测试了模块的寄存器读写、中断触发和不同协议下的数据传输，仿真结果表明SSI接口IP核设计正确，功能符合设计要求。
[Abstract]:In recent years, with the rapid development of SOC design industry, its design complexity is increasing. SoC design field is faced with these two challenges. One is IP reuse technology, which aims at design reuse. The other is IP interconnection technology based on reusable IP core. Therefore, the research of IP multiplexing technology is of great significance in SOC design industry. Synchronous serial interface technology is a high-speed full-duplex synchronous serial communication bus with simple circuit. It is widely used in all kinds of SOC design. The universal synchronous serial interface IP core, which supports three serial protocols, SPI SSP and Microwire, is designed in this paper. It can be configured for master-slave mode to communicate with the external serial device. This flexible configuration and versatility are in line with the development direction of SOC design technology and have high practical value. With the popularization of IP reuse technology, the on-chip bus technology has been developed rapidly. This paper analyzes and compares the technical characteristics of Wishbo bus, which is simple, flexible, powerful, and has many third party support. Especially, the APB advanced peripheral bus in the AMBA bus architecture has the advantages of simple technology, low power consumption and strong practicability, and has a broad application prospect. According to the top-down design idea, the design method of synchronous serial interface IP core based on APB bus is discussed. Firstly, the design goal and requirement are analyzed, the external input and output interface of module is defined, and then the sub-module is divided according to the design function. The complete block diagram of IP core module, the detailed port and register description are given. Then, the specific functions and design ideas of each sub-module of IP core are discussed in detail. According to the verification plan, the RTL code of SSI interface IP core is simulated with Modelsim, and the register reading and writing, interrupt triggering and data transmission under different protocols are tested. The simulation results show that the design of SSI interface IP core is correct. The function meets the design requirements.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP336;TN47

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