众线程宽向量体系结构建模与性能分析

发布时间：2018-02-28 05:40

本文关键词： MTV体系结构模拟器多线程向量　出处：《国防科学技术大学》2012年硕士论文　论文类型：学位论文

【摘要】：随着单核微体系结构的不断改进，程序的指令级并行性已基本上开发殆尽，目前国际上微处理器的主要发展方向是发掘程序的任务级并行性和数据级并行性。本文试图在传统的单核体系结构基础上，深入发掘任务级并行性和数据级并行性，从多个层面提升微处理器性能。本文提出了面向科学计算的众线程宽向量（Many-Thread wide Vector，MTV）体系结构，能够同时开发程序的指令级并行性、任务级并行性和数据级并行性。本文的主要工作包括两个方面，即MTV体系结构建模和MTV体系结构的性能分析。首先，本文对MTV体系结构进行了功能建模和性能建模，，形成了一款执行驱动的MTV体系结构全系统模拟器。功能建模方面，该模拟器建模了MTV体系结构的寄存器、存储器和指令执行引擎，支持引导未经修改的操作系统，并且采用了指令译码缓冲和地址翻译缓冲等多种优化技术提升性能。性能模拟方面，建模了一条支持硬件多线程的乱序执行流水线，建模了分支预测、乱序执行、硬件多线程、Cache层次和片上互连网络等多种微体系结构部件。MTV模拟器采用模块化设计思想，利用动态链接技术，实现了模拟器各部件模型的动态加载，使得模拟器具有很高的灵活性。其次，本文在MTV模拟器内实现了一个片上存储系统的Profiling框架，并在此基础上对MTV体系结构的存储系统进行了初步研究和性能分析，包括多线程对访存延迟的容忍程度和向量存储对存储结构的影响两个方面。基于对实验数据的分析，提出了一种适合标量和向量混合存储的存储器改进方案，并进行了一定的性能分析。
[Abstract]:With the continuous improvement of the single-core microarchitecture, the instruction level parallelism of the program has basically been developed. At present, the main development direction of microprocessor in the world is to explore the task level parallelism and data level parallelism of programs. This paper attempts to explore the task level parallelism and data level parallelism on the basis of the traditional single core architecture. In this paper, we propose a multithread wide vector many-Thread wide VectorMTV architecture for scientific computing, which can simultaneously develop the command level parallelism, task level parallelism and data level parallelism of programs. The main work of this paper includes two aspects: modeling of MTV architecture and performance analysis of MTV architecture. First of all, the function modeling and performance modeling of MTV architecture are carried out, and an executive-driven MTV architecture full-system simulator is formed. In terms of functional modeling, the simulator models the register of MTV architecture. Memory and instruction execution engine, supporting the boot of unmodified operating system, and using a variety of optimization techniques such as instruction decoding buffer and address translation buffer to improve performance. In this paper, we model pipeline, which supports hardware multithreading, model branch prediction, scramble execution, hardware multithreading Cache hierarchy and on-chip interconnection network. MTV simulator adopts modularization design idea. The dynamic link technology is used to realize the dynamic loading of each component model of the simulator, which makes the simulator have high flexibility. Secondly, a Profiling framework of on-chip storage system is implemented in the MTV simulator, and the storage system of MTV architecture is studied and analyzed on this basis. This paper includes two aspects: the tolerance of multithreading to memory access delay and the effect of vector storage on memory structure. Based on the analysis of experimental data, a memory improvement scheme suitable for scalar and vector hybrid storage is proposed. A certain performance analysis was carried out.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332

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