EDGE处理器中分布式存储结构研究

发布时间：2018-02-28 10:27

本文关键词： EDGE处理器分布式存储指令队列　出处：《哈尔滨工业大学》2013年硕士论文　论文类型：学位论文

【摘要】：广泛存在的传统集总式结构已经严重限制乱序超标量处理器的性能提升。特别是针对EDGE（Explicit Data Graph Execution）体系结构的微处理器，尽管取指单元、执行单元、寄存器单元都采用了分布式结构，但是，存储指令单元——Load-Store-Queue，仍然是一种集总式的设计结构。这种集总式结构拥有很差的可扩展性特点，限制了相关性检查的处理效率，阻碍了处理器性能的提高。本文主要通过运用M5-EDGE模拟器，针对集总式Load-Store-Queue的特征进行实现并加以研究分析，评估集总式Load-Store-Queue所面临的诸多问题和缺陷。评估得出，集总式Load-Store-Queue处理效率很低，一次检索项数较多，延时和功耗也相应较高，，并且，可扩展性差，不能一味地与指令窗口数保持对等的项数增加。同时，研究现代应用程序的存储指令相关性特点，发现加速相关指令的执行效率将大大提高处理器性能。在M5-EDGE模拟器上设计实现分布式Load-Store-Queue结构。使得每个执行单元都包含一个独立的Load-Store-Queue单元。针对甚块动态Deep映射算法，每个甚块独立进行甚块内相关性检查操作，并在流水线递交级进行甚块间的相关性检查.将递交延时和相关性检查延时重叠以减少总延时，并且设计重取指机制以处理甚块间违例的恢复工作。进行分布式Load-Store-Queue性能评估。相对于集总式结构设计，分布式结构面积并无明显增加，同时，增加相关性检查带宽和减少检查延时，平均效率提高64至256倍，而且也相应的降低了相关性检查的功耗。在综合评估之后，分布式Load-Store-Queue的优势是显而易见的，彻底摒弃了集总式Load-Store-Queue结构的缺点。虽然运行测试程序后发现性能有所降低，这主要是由于重取指的机制带来的性能损害，可以通过其他机制进行优化，而且可优化的策略很多，在充分选择优化策略之后，会对EDGE体系结构微处理器性能产生很好的影响。
[Abstract]:The widespread traditional lumped architecture has severely limited the performance improvement of scrambled superscalar processors. The register unit is distributed, but the memory instruction unit, Load-Store-Queue, is still a lumped structure, which has poor extensibility and limits the processing efficiency of correlation checking. It hinders the improvement of processor performance. In this paper, we use M5-edge simulator to realize and analyze the characteristics of lumped Load-Store-Queue, and evaluate the problems and defects faced by lumped Load-Store-Queue. It is concluded that lumped Load-Store-Queue is very inefficient. The number of items in a single retrieval is more, the delay and power consumption are also higher, and the expansibility is poor, so the number of items can not be kept equal to the number of instruction windows blindly. At the same time, the characteristics of memory instruction correlation of modern application programs are studied. It is found that accelerating the execution efficiency of related instructions will greatly improve processor performance. The distributed Load-Store-Queue structure is designed and implemented on the M5-edge simulator, which makes each execution unit contain an independent Load-Store-Queue unit. For the very block dynamic Deep mapping algorithm, each very block independently performs the very block correlation checking operation. In order to reduce the total delay, we also design a refetch mechanism to deal with the recovery work between the very block violations. To evaluate the performance of distributed Load-Store-Queue. Compared with lumped structure design, the area of distributed structure does not increase significantly. At the same time, it increases the bandwidth of correlation check and reduces the check delay, and the average efficiency is increased 64 to 256 times. After comprehensive evaluation, the advantages of distributed Load-Store-Queue are obvious, and the shortcomings of lumped Load-Store-Queue structure are completely abandoned. This is mainly due to the performance damage caused by the mechanism of reindication, which can be optimized by other mechanisms, and there are many strategies that can be optimized. After the optimization strategy is fully selected, it will have a good impact on the performance of the EDGE architecture microprocessor.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333

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