基于Petri网的ASIP流水线研究

发布时间：2018-02-28 15:47

  本文关键词： Petri网 专用指令集处理器 流水线 PNML　出处：《武汉纺织大学》2014年硕士论文　论文类型：学位论文

【摘要】：专用指令集处理器(ASIP)是一种新型的具有处理器结构的芯片，具有可定制性，应用在某些特定领域，通过功能定制，能对嵌入式系统进行优化，提高嵌入式设备的执行效率，随着嵌入式领域的发展，ASIP得到了广泛应用。 随着ASIP应用面的扩大，对ASIP的设计周期，设计成本等非功能性要求越来越高，而流水线结构层设计是ASIP设计中最复杂的部分之一，传统的ASIP流水线设计方法已经无法满足要求，本文针对传统设计方法设计周期长，更改底层逻辑的工作量大的不足，探讨了一种基于“描述-综合”的设计方法学，对ASIP流水线微结构进行建模，用可执行描述语言对模型描述，通过逻辑综合，生成RTL级的HDL描述，采用这种设计方式，能快速的对流水线结构验证和优化，，更改流水线结构只需要修改上层的模型描述，自动映射生成下层流水线结构，减少了设计者工作量，缩短了ASIP设计周期。 本文遵循“描述-综合”的设计方法学，采用Petri网对ASIP流水线进行建模，给出了三种不同架构的流水线Petri网模型，用可执行的PNML(Petri网标记语言)描述语言对流水线模型进行描述，利用自行设计完成的流水线集成开发环境，对OTA架构的流水线模型进行动态仿真验证，完成逻辑综合后，Petri网流水线模型的PNML描述映射成为RTL级的HDL描述，通过Altera QuartusⅡ对HDL代码进行调试，仿真。最后下载到FPGA（CycloneⅢ系列）开发板运行观察结果。
[Abstract]:ASIP (Special instruction set processor) is a new type of chip with processor architecture, which can be used in some special fields. Through function customization, embedded system can be optimized and the execution efficiency of embedded device can be improved. With the development of embedded field, ASIP has been widely used. With the expansion of ASIP application area, the non-functional requirements of ASIP design cycle, design cost and so on are becoming higher and higher. Pipeline structural layer design is one of the most complex parts in ASIP design. The traditional ASIP pipeline design method has been unable to meet the requirements. This paper discusses a design methodology based on "description and synthesis", aiming at the shortage of long design period and heavy workload of changing the underlying logic in the traditional design method. Modeling the ASIP pipeline microstructure, describing the model with executable description language, generating RTL level HDL description by logic synthesis, using this design method, we can quickly verify and optimize pipeline structure. Changing pipeline structure only needs to modify the model description of the upper layer, and automatically map to generate the lower-layer pipeline structure, which reduces the designer's workload and shortens the ASIP design cycle. In this paper, according to the design methodology of "description and synthesis", ASIP pipeline is modeled by using Petri net, and three kinds of pipeline Petri net models with different structures are given. Pipeline model is described by using executable PNML(Petri net markup language (PNML(Petri net markup language), and by using the integrated development environment of pipeline, which is designed and completed by ourselves, a dynamic simulation is carried out to verify the pipeline model of OTA architecture. The PNML description of pipeline model of logic synthesis is mapped to RTL level HDL description. The HDL code is debugged and simulated by Altera Quartus 鈪

本文编号：1547960