栅介质氧化层缺失缺陷的形成原因及解决方案

发布时间：2018-03-02 19:07

本文选题：原位水蒸气生成(ISSG)　切入点：栅介质氧化层缺失　出处：《半导体技术》2015年03期 　论文类型：期刊论文

【摘要】：氮氧化技术是45 nm及以下技术节点栅介质制备的关键工艺,严格控制由氮氧化工艺所诱发的界面缺陷是提高栅介质质量的重点。研究了形成栅介质氧化层缺失缺陷的原因,并提出了解决方案。结果表明,原位水蒸气生成(ISSG)热氧化形成栅介质氧化层后的实时高温纯惰性氮化热处理工艺是形成栅介质氧化层缺失缺陷的主要原因;在实时高温纯惰性氮化热处理工艺中引入适量的O2,可以消除栅介质氧化层的缺失缺陷。数据表明,引入适量O2后,栅介质氧化层的界面陷阱密度(Dit)和界面总电荷密度(ΔQtot)分别减少了12.5%和26.1%;p MOS器件负偏压不稳定性(NBTI)测试中0.1%样品失效时间(t0.1%)和50%样品失效时间(t50%)分别提高了18%和39%;32 MB静态随机存储器(SRAM)在正常工作电压和最小工作电压分别提高了9%和13%左右。
[Abstract]:Nitrogen oxidation technology is the key technology for the preparation of gate dielectric at 45 nm and below. The key to improve the quality of gate dielectric is to strictly control the interface defects induced by nitrogen oxidation process. The reasons for the defect of gate oxide layer are studied. The results show that the real time high temperature pure inert nitriding heat treatment process after thermal oxidation of gate dielectric oxide is the main reason for the defect of gate dielectric oxide layer. The defect of oxide oxide in gate dielectric can be eliminated by introducing proper amount of O _ 2 in the process of real time high temperature pure inert nitriding heat treatment. The data show that after introducing appropriate amount of O _ 2, the defect of oxide layer in gate dielectric can be eliminated. The interface trap density and total interface charge density (螖 Qtott) of the gate oxide layer decreased by 12.5% and 26.1 respectively. The failure time of 0.1% samples and 50% samples were increased by 18% and 393232 respectively in the measurements of negative bias instability of 0.1% samples and 50% samples, respectively. MB static random access memory (SRAM) increases the normal and minimum operating voltages by about 9% and 13% respectively.
【作者单位】：上海华力微电子有限公司;
【基金】：国家重大科技02专项资助项目(2011ZX02501)
【分类号】：TP333

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