内存容限测试的分析及优化方案

发布时间：2018-03-02 22:07

本文选题：内存总线　切入点：容限测试　出处：《上海交通大学》2012年硕士论文　论文类型：学位论文

【摘要】：随着计算机系统的运算速度的日新月异，如何更好地评估信号数量众多、时序复杂的内存总线越来越成为主板厂商亟待解决的问题。本文提出并实现了一种内存容限测试系统的优化方案，较好地解决了现有测试系统在测试时间、测试准确度和测试可扩展性等方面的问题。现有的容限测试系统，类似于对内存条本身的评估一样，采用了RST Pro/Pro2card测试系统中的所有物理内存地址空间，导致压力测试的时间过长。其采用的单一步进的电压调节策略，不能较好地解决电压调节次数和测试精度的矛盾，既增加了容限测试的测试用时，测试精度和稳定性又需要提升。同时现有测试系统还受限于主机系统与测试主板的串口连接，并行测试的主机数量有限，也无法实现远程控制和远程调试等较高级的操作。本文实现的优化方案，采用了边界定位的策略，，利用内存映射将最易出错的边界区域作为目标测试区域，通过减少内存测试范围大大降低了压力测试的时间；多阶段的电压调节策略结合多处理器核测试技术既减少了电压调节次数又提高了测试精度和稳定性；基于TCP/IP的网络化测试环境增加了测试的可扩展性。实验结果证明该优化方案大幅度改善了内存容限测试的并行性和测试用时，其加速比分别达到了3倍与5倍左右，实现了预期目标。
[Abstract]:With the rapid development of computer system, how to better evaluate the number of signals, Memory bus with complex timing has become an urgent problem to be solved by motherboard manufacturers. In this paper, an optimization scheme of memory tolerance testing system is proposed and implemented, which solves the test time of the existing test system. Test accuracy and test scalability and other aspects of the problem. The existing tolerance test system, similar to the evaluation of the memory bar itself, uses all physical memory address spaces in the RST Pro/Pro2card test system, which results in a long time for pressure testing. It can not solve the contradiction between voltage regulation times and test accuracy. It not only increases the test time of tolerance test, but also needs to improve the test accuracy and stability. At the same time, the existing test system is limited by the serial port connection between the host system and the test motherboard. The number of parallel test hosts is limited, and the more advanced operations such as remote control and remote debugging can not be realized. In the optimization scheme, the strategy of boundary location is adopted. The most error-prone boundary area is taken as the target test area by memory mapping, and the time of stress testing is greatly reduced by reducing the memory test range. The multi-stage voltage regulation strategy combined with the multi-processor core test technology not only reduces the voltage regulation times, but also improves the test accuracy and stability. The network test environment based on TCP/IP increases the scalability of the test. The experimental results show that the optimization scheme greatly improves the parallelism of memory tolerance testing and the test time, and the speedup ratio is about 3 times and 5 times, respectively. The expected goal has been achieved.
【学位授予单位】：上海交通大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333

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