适用于DDR SDRAM的控制器设计

发布时间：2018-03-03 04:39

本文选题：DDR　切入点：SDRAM　出处：《西安电子科技大学》2012年硕士论文　论文类型：学位论文

【摘要】：现代电子产品随着技术的迅速发展已呈现多样化，在各类的电子产品中均追求着多功能、高性能、低功耗，而整个产品对其主存储设备要求也是越来越高。DDR SDRAM（Double Data Rate SDRAM，双倍数据率同步动态随机存储器）以其高速率、大容量和良好的兼容性在这些需求存储设备的领域得到了相当广泛的应用。针对不同的系统要求，在选择器存储单元时有不同的取舍，比如，高性能计算机，其要求高频率以及高带宽，这样DDRII或者DDRIII都是很不错的选择，但是对嵌入式为系统而言，高性能就不是唯一的要求，其成本和稳定性也必须考虑在其中，经过综合考虑还是选择DDR SDRAM芯片，DDRIII成本太高，DDRII对电路板的要求很高，即在制作能够适用DDRII的电路板的成本就比较高。所以就目前而言虽然DDRII和DDRIII在性能方面有一定的优势，但以其高成本，人们在选择嵌入式的存储单元时还是倾向于DDR SDRAM。而DDR SDRAM和外设间需要一个桥梁，DDR SDRAM控制器正是起着这一重要的作用，所以研究设计DDRSDRAM控制器的设计有着极其重要的价值和意义。本文首先介绍了DDR SDRAM存储器的工作原理，在此基础之上给出了DDRSDRAM的指令以及典型的操作时序；按照JEDEC工业标准给定的时序要求对DDRSDRAM进行了总体模块的设计以及各小模块的划分，重点对DDR SDRAM的关键技术进行了详细的分析；采用自顶而下的设计方法，用Verilog HDL硬件描述语言进行控制器的实现，最后用仿真工具进行了前仿真和后续仿真，用Xilinx ISE进行了综合和布局布线，通过验证表明控制器的设计达到了预期的设计要求，符合一定的设计的规范。本文设计的控制器接口简洁，充分利用了FPGA中时钟管理资源，使得设计的复杂程度有一定的简化，，而且设计中的操作简单又能满足特定的DDR SDRAM控制，具有很强的适用性。
[Abstract]:With the rapid development of technology, modern electronic products have been diversified, and they are pursuing multifunction, high performance and low power consumption in all kinds of electronic products. The demand of the whole product for its main storage device is also getting higher and higher. DDR SDRAM(Double Data Rate SDRAM, double data rate synchronous dynamic random access memory (DRAM) with its high speed, Large capacity and good compatibility are widely used in these areas of demand storage devices. For different system requirements, there are different trade-offs when selecting storage units, such as high-performance computers, It requires high frequency and high bandwidth, so DDRII or DDRIII is a good choice, but for embedded systems, high performance is not the only requirement, its cost and stability must also be considered. After comprehensive consideration or selection of DDR SDRAM chip, the cost of DDR III is too high. The cost of making a circuit board that can be applied to DDRII is very high, that is, the cost of making a circuit board that can be applied to DDRII is relatively high. So at present, although DDRII and DDRIII have some advantages in performance, However, because of its high cost, people still prefer DDR SDRAM when they choose embedded memory cells. The need for a bridge between DDR SDRAM and peripheral devices plays this important role. So it is of great value and significance to study the design of DDRSDRAM controller. This paper first introduces the working principle of DDRSDRAM memory, and then gives the instruction of DDRSDRAM and the typical operation timing. According to the timing requirement of JEDEC industry standard, the overall module design and the partition of each module are carried out, the key technology of DDRSDRAM is analyzed in detail, and the top-down design method is adopted. The controller is implemented with Verilog HDL hardware description language. Finally, the pre-simulation and follow-up simulation are carried out with simulation tools, and the synthesis and layout routing with Xilinx ISE are carried out. The verification results show that the controller design meets the expected design requirements. Conform to certain design specifications. The controller designed in this paper is simple in interface, makes full use of the clock management resources in FPGA, simplifies the complexity of the design, and the operation in the design is simple and can satisfy the specific DDR SDRAM control, so it has strong applicability.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333

【引证文献】