容错处理器阵列的并行重构及VHDL实现

发布时间：2018-03-05 03:14

本文选题：处理器阵列　切入点：重构　出处：《小型微型计算机系统》2015年02期 　论文类型：期刊论文

【摘要】：网格连接的处理器阵列是一种应用广泛的高性能体系结构,而容错处理器阵列的重构技术是近年来的研究热点之一.现有的研究多数集中在串行重构算法上,忽视了该结构重构时内在的可并行性.本文根据阵列结构的特点设计了一种基于VHDL语言的重构算法,该算法从第一行的各个无故障处理器单元同时向下选路,具有潜在的并行性,.实验结果表明,与现有的串行算法相比,本文提出的并行算法同样能够生成最大规模的目标阵列并且当物理阵列大小为48×48,本文提出的并行算法加速重构将近20倍.
[Abstract]:Grid connected processor array is a widely used high-performance architecture, and the reconstruction technology of fault-tolerant processor array is one of the research hotspots in recent years. In this paper, we design a reconstruction algorithm based on VHDL language according to the characteristics of the array structure. The algorithm selects the path from each fault-free processor unit in the first line at the same time. The experimental results show that, compared with the existing serial algorithms, The parallel algorithm proposed in this paper can also generate the largest target array. When the physical array size is 48 脳 48, the parallel algorithm proposed in this paper accelerates reconstruction by nearly 20 times.
【作者单位】：天津工业大学计算机科学与软件学院;天津大学计算机科学与技术学院;
【基金】：国家自然科学基金项目(61173032,61070136)资助
【分类号】：TP332

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