高效异步FIFO的设计实现

发布时间：2018-03-06 09:29

本文选题：FIFO　切入点：ASIC　出处：《湖南大学》2013年硕士论文　论文类型：学位论文

【摘要】：异步FIFO（FirstInFirstOut）是一种先进先出的存储器件，可以实现在不同时钟域之间进行数据的传递。异步FIFO的应用场景十分广泛，不仅能满足现代国防、航天航空等领域应用的需要，还可用于数据采集和图象处理等其它方面。相比于同步集成电路设计，异步集成电路具有低功耗、高性能和便于模块化设计等优点，，目前在集成电路的设计中已经被各大公司所采用。特别是异步时钟域数据之间的传输是一个重要的问题，采用异步FIFO是解决这一问题的重要手段。空/满信号的产生以及亚稳态的问题是异步FIFO设计中的两个难点。首先：空/满信号的产生，是通过比较读写地址指针来产生的，当读写地址指针相同时，FIFO无法确定处于空状态还是满状态；其次：亚稳态问题，由于读写地址处于不同的时钟域之中，比较之前需要对地址进行同步，由于地址指针是多位的，在同步过程中不可避免的会产生亚稳态的问题。针对存在的两个问题，本设计通过采用地址附加位和格雷码指针代替二进制码地址的方式进行了有效的解决，即在读写地址前增加一位附加位来判断是空状态还是满状态。在空满状态的界定时增加了保留空间（Reserve）这一参数，从而增强了FIFO的稳定性。采用格雷码指针代替二进制码地址，并且采用可配置的同步电路解决这一问题。还通过对FIFO时钟进行合理的利用，在读写控制模块不工作时，相应的时钟停止，直到开始工作时，时钟重新启动，从而满足了高效率的要求。本设计模块采用VerilogHDL代码进行编写，使用SynopsysVCS进行功能通读仿真，并用Xilinx的FPGA进行功能验证，由于本FIFO设计模块是话音处理器分合路模块的一部分，将与其他模块整合在一起，综合及布局布线采用中芯国际（SMIC）0.18μmCMOS工艺库，最终根据项目要求实现了流片。通过实际测试结果表明：该话音处理器的计算误差低于4%；在工作电压为1.8V的情况下，其平均功耗约为1.18mW/MHz，本设计在稳定性、功耗、速度上都达到了预期的要求。
[Abstract]:Asynchronous FIFO (first in first output) is a kind of first in first out memory device, which can transfer data between different clock domains. Asynchronous FIFO is widely used in many fields, which can not only meet the needs of modern defense, aerospace and other applications. It can also be used in data acquisition and image processing. Compared with synchronous integrated circuit design, asynchronous integrated circuit has the advantages of low power consumption, high performance and easy modular design. At present, the design of integrated circuits has been adopted by many companies, especially the transmission between asynchronous clock domain data is an important problem, the use of asynchronous FIFO is an important means to solve this problem. The generation of empty / full signal and the problem of metastable state are two difficulties in asynchronous FIFO design. Firstly, the generation of empty / full signal is produced by comparing the read and write address pointer. When the read-write address pointer is the same, the FIFO can not determine whether it is empty or full. Secondly, the metastable problem, because the read-write address is in different clock fields, the address needs to be synchronized before comparison, because the address pointer is multi-bit. The problem of metastable state is inevitable in the process of synchronization. In order to solve the two problems, the method of adding address bit and Graycode pointer instead of binary code address is used to solve the problem. That is, adding an additional bit before reading and writing to determine whether the empty state is empty or full. The parameter of reserved space is added in the definition of empty full state, which enhances the stability of FIFO. The gray code pointer is used instead of binary code address. And the configurable synchronous circuit is used to solve this problem. Through the reasonable use of the FIFO clock, the corresponding clock stops when the read-write control module does not work, and the clock restarts when it starts to work. Thus, it meets the requirement of high efficiency. This design module uses VerilogHDL code to write, uses SynopsysVCS to carry on the function read through the emulation, and uses the Xilinx FPGA to carry on the function verification, because this FIFO design module is a part of the voice processor divider module, will integrate with the other modules together, The synthesis and layout wiring is based on the SMIC SMIC 0.18 渭 mCMOS process library. Finally, the flow sheet is realized according to the requirements of the project. The actual test results show that the calculation error of the voice processor is less than 4 parts, and the working voltage is 1.8 V. The average power consumption is about 1.18mW / MHz. the design meets the expected requirements in terms of stability, power consumption and speed.
【学位授予单位】：湖南大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333

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