众核片上私有型末级Cache共享化架构设计与实现

发布时间：2018-03-07 20:17

本文选题：众核处理系统　切入点：片上存储架构　出处：《上海交通大学》2013年硕士论文　论文类型：学位论文

【摘要】：应用复杂度的不断上升以及芯片功耗的制约，使得单核、多核处理系统逐渐难以满足需要；处理数量更多的众核处理系统受到了越来越多的关注。然而，更多的处理核数量，却对作为处理系统性能关键因素的片上存储架构的设计带来了新的挑战：其一，处理核数量增多导致芯片规模上升、片上访存延时上升；其二，众核处理系统中对应用细粒度并行化而衍生的共享化数据模型，导致单个处理核存储空间需求上升。面对新挑战，传统多核片上存储架构均存在缺陷：共享型末级Cache架构将引起大量片上网络通信，且其相对单个处理核的模块化与可扩展性较差；私有型末级Cache架构，其单个处理核的等效存储空间较小，导致对片外存储单元的访存过多；Cooperative Caching架构，为请求数据块的处理核所提供的选择较少，易导致长距离、横跨芯片的数据块访存。针对众核处理系统所带来的新挑战及传统架构应对时的不足，本文提出了众核片上私有型末级Cache共享化架构。以未来众核系统中更具潜力的私有型末级Cache架构为基础，通过将单个处理核的被替换数据块保留于片上其他处理核中，并允许片上各处理核间的数据块互相访存，实现私有型末级Cache架构的共享化，提高单个处理核存储空间的等效容量。通过对被替换数据块在片上保留多个副本，为该数据块的请求处理核提供更多选择，得以从更合适的地方获得数据块。同时，通过基于阈值在线动态调整的被替换数据块保留数量判决算法与基于存储资源利用率在线监测的被替换数据块保留位置选择算法，分别从保留数量与保留位置两个维度，细粒度地控制被替换数据块的多副本保留，，减少保留行为对其他处理核存储空间的影响。本文在描述了所提出架构具体实现方案的基础上，对其硬件实现代价作了分析：本架构硬件额外开销约为4.35%~8.20%。同时，本文利用GEM5全系统仿真平台，以64核众核处理系统为例，将本文所提出架构，与传统架构进行对比。性能分析结果显示：本架构在片上网络通信负荷上，相比共享型末级Cache架构减少78.6%，相比私有型末级Cache架构略有增加，相比Cooperative Caching架构减少11.9%；在片外存储单元访存负荷上，相比私有型末级Cache架构下降25.6%，相比Cooperative Caching架构下降6.5%；在众核处理系统整体处理性能上，相比共享型末级Cache架构均提升59.5%，私有型末级Cache架构最好情况提升11.9%、平均提升6.2%；Cooperative Caching架构最好提升11.2%、平均提升5.3%。综合上述硬件实现代价及性能分析结果，证明了本架构能有效提升片上存储架构及整个众核处理系统性能；同时，证明了本文提出的从保留数量与保留位置对被替换数据块保留行为进行控制的算法的有效性。
[Abstract]:With the increasing complexity of applications and the restriction of chip power consumption, it is difficult for single-core and multi-core processing systems to meet the demand, and more and more multi-core processing systems have attracted more and more attention. However, it brings new challenges to the design of on-chip memory architecture, which is a key factor in processing system performance. First, the increase in the number of processing cores leads to an increase in chip size, and the increase in chip petition latency. The shared data model derived from fine-grained parallelization of applications in multi-kernel processing systems leads to an increase in storage space requirements for single processing cores. The traditional multi-core on-chip storage architecture has some defects: the shared-end Cache architecture will cause a large amount of on-chip network communication, and its modularization and scalability are poor compared with a single processor core, and the private Cache architecture of the last stage. The equivalent storage space of the single processing core is small, which leads to excessive memory access to the off-chip memory unit and cooperative Caching architecture, which provides less choice for the processing core of the request data block. It is easy to lead to long distance access to the data block across the chip. In view of the new challenges brought by the multikernel processing system and the shortcomings of the traditional architecture, this paper proposes a private Cache sharing architecture on the multikernel chip, which is based on the more potential private Cache architecture in the future multikernel system. By retaining the replaced data blocks of a single processing core in other processing cores on a chip, and allowing the data blocks between the processing cores on a chip to visit each other, the sharing of the private Cache architecture is realized. Increases the equivalent capacity of the storage space of a single processing core. By retaining multiple copies of the replaced data block on the chip, it provides more options for the request processing core of the data block, allowing it to obtain the data block from a more appropriate place. At the same time, Based on the online dynamic adjustment of threshold, the decision algorithm of the reserved number of the replaced data block and the algorithm of selecting the reserved position of the replaced data block based on the online monitoring of the utilization of the storage resources are used to select the reserved position of the replaced data block, respectively from two dimensions: the reserved number and the reserved position. The multi-replica reservation of the replaced data block is controlled fine-grained to reduce the effect of the reservation behavior on the storage space of other processing cores. On the basis of describing the concrete implementation scheme of the architecture, this paper analyzes the cost of the hardware implementation: the extra cost of the architecture hardware is about 4.35 and 8.20.At the same time, this paper makes use of the GEM5 full-system simulation platform and takes 64 core multi-core processing system as an example. Compared with the traditional architecture, the performance analysis shows that the architecture is 78.6 less than the shared Cache architecture and slightly more private than the private Cache architecture. Compared with the Cooperative Caching architecture, there is a decrease of 11.9% in the out-of-chip memory access load, 25.6% lower than the private Cache architecture, 6.5% lower than the Cooperative Caching architecture, and 6.5% lower than the Cooperative Caching architecture, and the overall processing performance of the multi-core processing system, Compared with the shared Cache architecture, the last level of Cache architecture is 59.5% higher, the private Cache architecture of the last level is 11.9% higher, the average 6.2U Caching architecture is improved 11.2cm, and the average increase is 5.3.The results of the above hardware implementation cost and performance analysis are summarized. It is proved that the proposed architecture can effectively improve the performance of the on-chip storage architecture and the entire multi-kernel processing system. At the same time, the effectiveness of the algorithm proposed in this paper to control the reserved behavior of the replaced data blocks from the retention number and the reserved position is proved.
【学位授予单位】：上海交通大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TN47;TP332

【共引文献】