低开销高可靠性电源门控SRAM设计

发布时间：2018-03-08 19:36

本文选题：静态随机存储器　切入点：电源门控　出处：《国防科学技术大学》2013年博士论文　论文类型：学位论文

【摘要】：随着半导体制造工艺的不断进步,晶体管的特征尺寸持续减小,微处理器设计已经从以Intel 4004(10um,1971年)为代表的微米设计时代进入到了当今以Intel酷睿i7 4770K(22nm,2013年)为代表的纳米设计时代。工艺的进步在带来高性能的同时,也使得微处理器的功耗持续增长,可靠性问题日益突出。功耗和可靠性已成为纳米设计时代首要考虑的问题。静态随机存储器(Static Random Access Memory,SRAM)是现代微处理器和片上系统中使用最广、数量最大、集成度最高的部件。庞大的数量使得SRAM阵列成为微处理器漏流功耗的主要来源。为了降低漏电流,电源门控技术被广泛的应用到SRAM阵列的设计中。为了提高集成度,SRAM设计往往采用最小尺寸进行,这使得其容易受到工艺偏差、器件老化等因素的影响,其中偏压温度不稳定性(Bias Temperature Instability,BTI)效应是近年来被认为对SRAM阵列影响最严重的可靠性问题之一。本文主要以低开销高可靠性的电源门控SRAM设计为目标,围绕着低开销的电源门控重启动电路设计、BTI效应对电源门控SRAM的影响和高可靠性的电源门控SRAM设计展开,文章的主要创新点和内容如下:1)设计了一种高效的电源门控电路重启动策略。电源门控电路重启动过程中的功耗和延时开销是该电路的主要开销来源。本文在电源门控电路中设计了一种电荷循环共享策略,它在有效降低电路状态转换过程中能量和延时开销的同时,也降低了电路重启动过程中的浪涌电流,减小了电源和地线网络的振荡,进而增加电路的可靠性。实验结果表明,在1.11%的面积开销下下,温度为25℃时,这一策略可以得到18.40%的唤醒能量开销减小量、3.27%的峰值浪涌电流减小量、9.73%的唤醒延时减小量。峰值浪涌电流的减小可以明显的减小地线振荡。2)提出了一个基于信号概率和活跃性概率的模型,用以评估正、负偏压温度不稳定性(Positive Bias Temperature Instability(PBTI)、Negative Bias Temperature Instability(NBTI))对电源门控SRAM的影响。实验表明,PBTI对电源门控SRAM的读和写操作影响明显。在PBTI、NBTI效应的共同作用下,106秒的工作时间可以使电源门控SRAM的静态噪声容限降低39.38%,写容限降低35.7%。利用CPU2000测试程序集的统计结果,我们发现本文提出的评估模型得到的静态噪声容限退化率比前人的结果小3.85%,更好的反映了电源门控技术对SRAM的影响。3)设计了一种低电压振荡的偏压温度不稳定性快速恢复电路。利用偏压不稳定性的恢复效应,该电路可以在细粒度上控制SRAM阵列快速进入或退出BTI恢复状态,减小电源门控SRAM阵列的性能退化。通过引入一条旁路电源线和一条旁路地线,可以将电路状态转换过程中主电源线和主地线上的振荡从100mV减小到10mV,从而大大的减小了振荡对邻近电路的影响,增加了可靠性。综上所述,通过电荷共享的重启动电路设计可以减小电源门控电路的启动开销;提出的信号概率和活跃性概率可以定量的分析BTI效应对电源门控SRAM的各种影响;利用低振荡恢复电路设计可以使得SRAM受应力作用而产生的BTI退化效应明显减弱,提高了电路的可靠性,同时也延长其使用寿命。所以,本文的研究有力的保证了电源门控SRAM设计的低开销和高可靠性,为电源门控SRAM设计进一步的广泛使用提供了支持。
[Abstract]:With the development of semiconductor manufacturing technology, the feature size of transistors is reduced continuously, the microprocessor design has been from a Intel 4004 (10um, 1971) as the representative of the micron design era into the Intel Core i7 4770K (22nm, 2013) - as the representative of the design era. The technological progress in bringing high performance at the same time also, the microprocessor power consumption continues to grow, reliability issues have become increasingly prominent. The power consumption and reliability have become the nano design era primaryconsideration. Static random access memory (Static Random Access Memory, SRAM) is a system of modern microprocessor chip and the most widely used, the largest number of components, the highest level of integration. The huge number of the SRAM the microprocessor array has become a major source of leakage power. In order to reduce the leakage current, power gating technology has been widely applied to the SRAM array design in order to improve. Integration, SRAM design is often used in the smallest size, which makes the process vulnerable to bias, effects of aging factors, including bias temperature instability (Bias Temperature, Instability, BTI) effect in recent years is considered one of the most serious impact on the reliability of the SRAM array. This paper is mainly to design high reliability power gating SRAM the low cost, around the reset circuit design of power gating low overhead, power gating design SRAM BTI effect on SRAM power gating and high reliability, the main innovations of the paper are as follows: 1) and a power gating circuit, the design of restart strategy. The power gating circuit start in the process of power consumption and delay cost is the main source of overhead of the circuit. The power gating circuit in the design of a charge cycle sharing strategy, which effectively To reduce the circuit state transition energy and delay overhead in the process at the same time, also reduce the inrush current during startup circuit, reduces the oscillation power and ground network, and increase the reliability of the circuit. The experimental results show that in the 1.11% area overhead under the temperature of 25 DEG C, this strategy can get 18.40% wake up the energy cost reduction, the peak surge current of 3.27% reduction, 9.73% reduction of the wakeup delay. The peak surge current decreases can significantly reduce ground oscillation of.2) is proposed based on the signal probability and active probability model to evaluate the positive and negative bias temperature instability (Positive Bias Temperature Instability (PBTI), Negative Bias Temperature Instability (NBTI)) of power gating SRAM. Experimental results show that the PBTI of power gating SRAM read and write operation is obvious. In PBTI, NBTI. The interaction should be under 106 seconds working time can make the static noise power gating SRAM margin decreased 39.38%, write tolerance reduces the statistical results of 35.7%. using CPU2000 test program set, we found that the static noise evaluation model proposed in this paper is the tolerance of degradation rate than before the 3.85% results, better reflect the power gating technique's effect on SRAM.3) to design a low voltage bias temperature instability oscillation fast recovery circuit. Using bias instability recovery effect, the circuit can control the SRAM array in the fine-grained quickly enter or exit the BTI recovery, reduce the performance degradation power gating SRAM array by introducing. A bypass power line and a by-pass line can be the main power line oscillation circuit state conversion process and the main ground decreased from 100mV to 10mV, which greatly reduces the vibration of Influence of adjacent circuit, increase the reliability of the design. To sum up, reset circuit through charge sharing can reduce the startup overhead power gating circuit; the signal probability and probability can put forward active quantitative analysis of BTI effect on SRAM power gating effect; recovery circuit design can make SRAM the effect of stress caused by low the oscillation of the BTI degradation effect decreased significantly, and improve the reliability of the circuit, but also prolong the service life. Therefore, the research in this paper to guarantee the power gating design of SRAM low overhead and high reliability, and provides support for power gating SRAM design is widely used in the future.

【学位授予单位】：国防科学技术大学
【学位级别】：博士
【学位授予年份】：2013
【分类号】：TP333

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