面向众核处理器的独立调试系统设计方法

发布时间：2018-03-09 12:49

本文选题：硅调试　切入点：片上网络　出处：《湖南大学学报(自然科学版)》2015年04期 　论文类型：期刊论文

【摘要】：基于片上网络(Network-on-Chip,NoC)技术的众核处理器正成为当前高性能处理器的设计焦点.传统的调试系统结构不能很好地应用于众核处理器体系结构,众核处理器中踪迹数据传输、调试事件传播、时间戳同步等方面均面临重大挑战.为解决上述问题,提出一种具有高带宽、低资源消耗的独立调试系统设计方法.该方法通过减少长互连线,提高了调试通道工作频率,以较少的互连线即可实现高带宽传输通道;同时调试组件采用分布式的对称结构,具有良好的可扩展性.在踪迹数据传输结构中,提出了一种带宽平衡的非侵入式踪迹数据导出方法,该方法通过软硬协同方式来配置踪迹通道仲裁的权重值,降低硬件复杂度.在调试事件的传播上,构建了与片上网络拓扑一致的事件传播网络,该网络在易于物理实现的同时具有事件传播延迟低的特点.在时间戳的同步方法上,提出了一种通过软硬件协同的时间同步方式,以很小的硬件代价实现了较精确的时间戳同步.
[Abstract]:Multi-core processor based on Network-on-ChipNOC (on-chip network) technology is becoming the focus of high performance processor design. The traditional debugging system structure can not be applied to the multi-core processor architecture and trace data transmission in multicore processor. Debugging event propagation and timestamp synchronization are all facing great challenges. In order to solve the above problems, an independent debugging system design method with high bandwidth and low resource consumption is proposed. The working frequency of debugging channel is improved, and the high bandwidth transmission channel can be realized with fewer interconnections. At the same time, the debug component adopts distributed symmetric structure, which has good scalability. In this paper, a bandwidth-balanced non-intrusive method for trace data export is proposed. The method configures the weight of trace channel arbitration in a soft and hard cooperative way and reduces the hardware complexity. An event propagation network, which is consistent with the on-chip network topology, is constructed. The network is easy to realize physically and has the characteristics of low event propagation delay. In the time stamp synchronization method, a time synchronization method based on hardware and software cooperation is proposed. More accurate timestamp synchronization is realized at a low hardware cost.
【作者单位】：国防科技大学计算机学院;
【基金】：国家自然科学基金资助项目(61202122,61402497,61173016)~~
【分类号】：TP332

【相似文献】