VLIW DSP处理器下累加计算优化方法

发布时间：2018-03-13 10:48

本文选题：VLIW　切入点：DSP　出处：《小型微型计算机系统》2015年08期 　论文类型：期刊论文

【摘要】：当今VLIW DSP处理器拥有的指令种类越来越多,它们大多利用单一指令来完成一组复杂的计算,从而提高相关操作的执行效率.无论是在现有数字信号处理程序中,还是使用各种优化手段之后的程序代码中,累加计算在VLIW DSP处理器运算的程序中总是频繁出现,编译器如何自动高效地识别并合成处理器特有的累加指令就变得尤为重要.提出一种VLIW DSP处理器下累加计算优化方法,算法可以自动合成目标处理器的累加指令,充分利用处理器体系结构和资源的特点.最后在BWDSP处理器上实现本文的优化算法,实验结果表明,本算法有效减小了程序累加部分的汇编代码长度,从而提高了BWDSP对累加计算的处理能力.
[Abstract]:Nowadays, VLIW DSP processors have more and more kinds of instructions, most of which use a single instruction to complete a complex set of calculations, thus improving the efficiency of the execution of related operations, whether in the existing digital signal processing programs, Still, in code that uses various optimizations, cumulative computing is often present in programs that are run by VLIW DSP processors. It is very important for the compiler to recognize and synthesize the specific accumulative instructions of the processor automatically and efficiently. This paper presents an optimization method of accumulative computation under the VLIW DSP processor, which can automatically synthesize the accumulative instructions of the target processor. Finally, the optimization algorithm is implemented on the BWDSP processor. The experimental results show that the algorithm can effectively reduce the length of assembly code in the cumulative part of the program. Thus, the ability of BWDSP to deal with accumulative computation is improved.
【作者单位】：中国科学技术大学计算机学院;安徽省计算与通信软件重点实验室;
【基金】：国家“核高基”重大专项项目(2009ZX01028-002-003-005)资助国家自然科学基金项目(60833004)资助
【分类号】：TP332

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