CMOS电流乘除法器及其应用研究

发布时间：2018-03-14 02:23

本文选题：电流模式信号处理　切入点：乘除法器　出处：《广西师范大学》2012年硕士论文　论文类型：学位论文

【摘要】：随着电流模式乘除法器的发展,CMOS电流模式乘除法器的研究和开发已逐渐成为主流趋势。CMOS电流模式乘除法器,与BJT乘除法器相比,在信号带宽、线性度、动态范围、信号处理能力等方面都有明显的优势,因而在信号处理中得到了广泛的应用,主要可以应用于模糊逻辑控制器、人工神经网络、可编程放大器、调制器、分相器、电流传输器、滤波器、正余弦综合器、密码学系统等。对于集成电路设计工程师来说,CMOS电流乘除法器可以作为非常有用的集成电路设计基本模块。基于平方根电路和平方/除法器电路设计的CMOS电流模式乘除法器具有线性度好、低功耗、结构简单、带宽宽、精度高等特点,在CMOS电流模式乘除法器中较具发展潜力。本论文研究了平方根和平方/除法器的电路实现及基于平方根电路和平方／除法器电路的CMOS电流模式乘除法器电路的设计与实现及其在模拟调幅器、可编程电流放大器、电调谐第二代电流传输器(ECCⅡ)等中的应用。本论文完成的工作及创新点主要包括： (1)以MOS管构成的跨导线性环路为基础,设计出电流模平方根电路以及平方／除法器电路,将平方根电路和平方/除法器电路连接起来,实现了一种新型高频高线性CMOS跨导线性电流模乘除法器电路。对提出的CMOS电流乘除法器的电路,使用CMOSO.35μm工艺参数,进行了HSPICE仿真。结果表明,该乘除法器电路能很好实现乘除法运算等功能。仿真结果证实了,提出的电路具有良好的线性特性、高频特性。该电路在3V的电源电压下工作时,-3dB带宽可达到35.1MHz,电源静态功耗为202.68μ W,输出电流范围为0～25.1μ A,非线性误差为0.85%,总谐波失真为0.14%。提出的乘除法器电路与Tanno、Lopez等提出的基于跨导线性原理的乘除法器电路相比,优点在于-3dB带宽提高了,功耗降低了,电源电压降低了,线性度提高了,并且采用了相对更先进的0.35μmCMOS工艺,可节约芯片面积。 (2)以上述提出的CMOS电流乘除法器电路为基础,电路结构及元件参数不变,对输入、输出信号进行选择,实现了提出的乘除法器在模拟调幅器、可编程电流放大器等中的应用。通过HSPICE软件仿真测试,证实了提出的应用方案的正确性。 (3)研究了一种新型简易CMOS电流乘除法器的电路及其在电流传输器电路设计中的应用。该电流模乘除法器电路同样是基于平方根电路和平方/除法器电路而组建成的,以此电路为基础,将该电路作为核心电路,加以应用,实现了可编程电流放大器,然后搭建电压到电流转换器、电流镜等其他电路,实现了一种新型的基于可编程电流放大器的CMOS第二代电调谐电流传输器ECCⅡ。该电路工作在很低的电源电压(±1.2V)下,电路增益持续可编程,线性调谐范围宽,Z端的输出阻抗高。这种电流传输器的电流传输比可以通过调节直流偏置电流而精确地控制。该电路采用0.35umCMOS工艺,使用HSPICE软件仿真。仿真结果证实了提出的ECCⅡ在线性度、频响、电调谐性和功耗方面具有良好的性能。
[Abstract]:With the development of the current mode multiplier AD633ARZ, research and development of CMOS current mode multiplier AD633ARZ has gradually become the mainstream trend of.CMOS current mode multipliers / dividers, compared with BJT in the multiplying unit, signal bandwidth, linearity, dynamic range, signal processing ability and other aspects have obvious advantages, so it has been widely used in signal processing, mainly used in fuzzy logic controller, artificial neural network, programmable amplifier, modulator, phase splitter, current conveyor filter, sine and cosine synthesizers, cryptography system. For integrated circuit design engineers, CMOS current multiplier AD633ARZ integrated circuit can be used as useful design basic modules.
Square and square root circuit / divider circuit design based on CMOS current mode multiplier divider has good linearity, low power consumption, simple structure, wide bandwidth, high accuracy, more development potential in the CMOS current mode multipliers / dividers. This paper studies the square root and square / divider circuit and current based on CMOS design model of square root circuit and multiplier divider circuit circuit and divider / square and its implementation in analog amplitude modulator, programmable current amplifier, electrically tunable second generation current conveyor (ECC II) application. The work and innovation of this paper mainly includes the complete:
(1) to MOS translinear loop is constituted based on Design of current mode circuit and divider / square square root circuit, connecting the square root circuit and square / divider circuit, the realization of a new high frequency linear CMOS translinear current mode multiplier AD633ARZ circuit. The proposed CMOS current division circuit the instruments, using CMOSO.35 m process parameters, HSPICE simulation was carried out. The results show that the multiplier divider circuit can realize multiplication and division functions. Simulation results demonstrate that the proposed circuit has linear characteristics, good high frequency characteristics. The circuit in the power supply voltage of 3V, -3dB bandwidth can reach 35.1MHz power supply, the static power consumption is 202.68 W, the output current range of 0 ~ 25.1 A, the nonlinear error is 0.85%, the total harmonic distortion for multiplier divider circuit and the Tanno 0.14%. proposed by Lopez based on the cross wire Compared with the multiplier AD633ARZ principle circuit, has the advantages of improving -3dB bandwidth, reduce the power consumption, the power supply voltage is reduced, improves the linearity, and the use of 0.35 mCMOS technology is relatively more advanced, can save the chip area.
(2) to CMOS current multiplier AD633ARZ circuit based on the above, the circuit structure and component parameters unchanged, the input, output signal selection is implemented in analog multiplier AD633ARZ modulator, programmable current amplifier in HSPICE. Through software simulation testing, confirmed the validity of the proposed scheme for applications.
(3) the study of a new type of circuit simple CMOS current multiplier divider and its application in current conveyor circuit design. The current mode circuit and multiplier AD633ARZ is also set up a square root circuit and divider / square based circuit, based on the circuit, the circuit as the core circuit, application, implementation programmable current amplifier, then set the voltage to current converter, current mirror and other circuit, realize a programmable current amplifier CMOS second generation current conveyor based on electrically tunable ECC II model. The circuit operates at very low power supply voltage (+ 1.2V), programmable gain circuit for linear tuning range. Wide, high output impedance of the Z terminal. The current transmission current conveyor ratio can be accurately controlled through adjusting the DC bias current. The circuit uses 0.35umCMOS technology, using HSPICE simulation software. The simulation results show that the proposed ECC II has good performance in the aspects of online degree, frequency response, electrical tuning and power consumption.

【学位授予单位】：广西师范大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332.22;TN402

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