基于CPCI总线的高速数据采集处理模块的设计

发布时间：2018-03-15 21:35

本文选题：高速信号采集　切入点：数字信号处理　出处：《电子科技大学》2013年硕士论文　论文类型：学位论文

【摘要】：高速发展的现代仪器仪表与自动测试技术促使着人们开发出高性能、高稳定性和易于系统集成的产品。数据采集与处理系统作为自动测试技术的核心，他的采样率、存储深度、分辨率和灵活及稳定性必然得到关注。而基于CompactPCIE、PXI/CompactPCI、VXI等总线的数据采集模块因其便于系统集成和稳定等特点，被广泛应用于自动测试测量和工业自动化领域。所以从提高采集系统带宽、实时采样率和存储深度等方面研究CPCI数据采集处理模块对整个测试系统有重大意义。本文主要从基于CPCI总线的高速数据采集处理模块的硬件实现和数字逻辑设计两个方面进行论述和分析，如数据采集存储逻辑设计和电路设计、DDR2SO-DIMM控制器设计、CPCI接口电路设计以及数字信号处理逻辑设计等。具体内容包括： 1.从研究如何提升系统采样率出发，得出基于时间交替并行采样技术，以1片双通道ADC来构架400MSPS采样设计方案。 2.分析采样时钟对采样性能的影响，并依据系统采样时钟设计理论，设计实现了1.5GHz高频时钟产生与转换的方案。 3.信号采集前端通道设计。实现高信噪比、高动态范围、信号增益与衰减可控的高速模拟信号通道； 4.根据系统存储深度和速度要求，，完成基于DDR2SDRAM SO-DIMM的硬件实现和DDR2控制器的逻辑设计，该控制器能够通过读取DDR2SDRAM SO-DIMM上的SPD信息实现时间参数和地址位宽自适用。 5.利用PLX公司的专用的PCI接口芯片PCI9054实现CPCI接口电路设计和本地逻辑接口实现。 6.完成过采样和数字滤波的逻辑设计，提高了采集精度和抗噪性能。该设计实现了DDR2SO-DIMM的控制，能够对采集的数据进行存储和数字化处理，满足设计指标要求，达到了预期目标。
[Abstract]:The rapid development of modern instrumentation and automatic testing technology has prompted people to develop high performance, high stability and easy system integration products. Data acquisition and processing system as the core of automatic testing technology, its sampling rate, storage depth, Resolution, flexibility and stability must be paid close attention to. The data acquisition module based on PXI / CompactPCI VXI bus is easy to integrate and stable. It is widely used in the fields of automatic measurement and industrial automation, so it is of great significance to study the CPCI data acquisition and processing module from the aspects of improving the bandwidth of the acquisition system, real-time sampling rate and storage depth, etc. This paper mainly discusses and analyzes the hardware implementation and digital logic design of high-speed data acquisition and processing module based on CPCI bus. Such as data acquisition and storage logic design and circuit design DDR2SO-DIMM controller design CPCI interface circuit design and digital signal processing logic design and so on. Specific elements include:. 1. Based on the study of how to improve the sampling rate of the system, a 400MSPS sampling design scheme based on the time alternating parallel sampling technique and a dual-channel ADC is proposed. 2. The influence of sampling clock on sampling performance is analyzed. According to the system sampling clock design theory, a 1.5 GHz high frequency clock generation and conversion scheme is designed and realized. 3. Design of front-end channel for signal acquisition. High speed analog signal channel with high signal-to-noise ratio, high dynamic range, controllable signal gain and attenuation; 4. According to the requirement of system storage depth and speed, the hardware implementation based on DDR2SDRAM SO-DIMM and the logic design of DDR2 controller are completed. The controller can realize time parameter and address bit width self-adaptation by reading SPD information on DDR2SDRAM SO-DIMM. 5. The design of CPCI interface circuit and the realization of local logic interface are realized by PCI interface chip PCI9054 of PLX company. 6. The logic design of oversampling and digital filtering is completed, and the acquisition accuracy and anti-noise performance are improved. The design realizes the control of DDR2SO-DIMM, can store and digitize the collected data, meet the requirements of the design index and achieve the expected goal.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP274.2;TP336

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