协同设计X86仿真指令集映射技术研究

发布时间：2018-03-18 08:19

本文选题：仿真技术　切入点：协同设计　出处：《解放军信息工程大学》2012年硕士论文　论文类型：学位论文

【摘要】：仿真技术能够有效地缓解处理器体系结构差异带来的软件兼容性问题，对RISC处理器特别是国产CPU的发展具有重要意义。在X86处理器占据较大市场份额、且拥有丰富软件资源的情况下，国产CPU要面向市场、走向应用就必须与X86平台的软件保持兼容。协同设计X86仿真技术兼顾了软件和硬件的优势，可获得较好的仿真效率，已经成为X86仿真技术发展的一个趋势。本文在广泛了解X86仿真技术研究现状的基础上，深入分析了当前X86仿真技术发展的性能瓶颈，针对协同设计X86仿真指令集映射技术中的关键问题进行了探讨，设计了指令翻译部件和翻译缓存部件。论文针对X86指令长度不定、指令格式多样等问题，提出了基于状态分拆的两级译码机制，与按字节译码方法相比，两级译码机制将译码过程划分为长度译码和操作数译码两个过程，，有效减少了X86指令译码带来的时钟开销；依据Pentium微程序设计思想和QEMU微操作设计思想，设计了基于LUT技术的指令集映射表Trans_lib，并通过寻址入口和功能入口完成指令翻译过程，有效减少了指令翻译过程中的时间和功耗开销；提出了硬件翻译缓存管理策略HTCM，将翻译缓存按比例划分为热代码区和普通代码区，分别采用FIFO和全清空策略管理，有效地减少了缓存碎片的产生，尽可能地延长了热代码在缓存中的驻留时间，提高了翻译缓存的命中率。最后，采用Verilog HDL硬件描述语言设计并实现了指令翻译部件和翻译缓存部件，并对其主要端口和功能进行了简要说明。验证和分析结果表明，论文所设计的指令翻译部件和翻译缓存部件可以成功地将X86指令集映射到Alpha指令集，并通过多种优化措施提高了指令集映射的性能。论文提出的两级译码机制相比于按字节译码机制最高可获得15.79%的性能提升；提出的HTCM策略的命中率相比于全清空和FIFO最高可获得17.43%和9.27%的性能提升。
[Abstract]:Simulation technology can effectively alleviate the software compatibility problem caused by the difference of processor architecture, and has great significance for the development of RISC processors, especially for domestic CPU. In the case of abundant software resources, if domestic CPU is to be market-oriented, it must be compatible with the software of X86 platform. The collaborative design of X86 simulation technology takes into account the advantages of software and hardware, and can obtain better simulation efficiency. X86 simulation technology has become a trend of development. On the basis of extensive understanding of the current research situation of X86 simulation technology, the performance bottleneck of current X86 simulation technology development is analyzed in depth. In this paper, the key problems in collaborative design X86 simulation instruction set mapping technology are discussed, and instruction translation components and translation cache components are designed. In order to solve the problems of variable length of X86 instructions and various instruction formats, a two-stage decoding mechanism based on state partition is proposed in this paper, which is compared with byte-by-byte decoding method. The two-stage decoding mechanism divides the decoding process into two processes: length decoding and Operand decoding, which effectively reduces the clock overhead brought by X86 instruction decoding, according to the idea of Pentium microprogramming and QEMU microoperation design. The instruction set mapping table based on LUT technology is designed, and the instruction translation process is completed by addressing entry and function entry, which effectively reduces the time and power consumption in instruction translation. A hardware translation cache management strategy is proposed. The translation cache is divided into hot code region and general code area according to the scale. FIFO and full emptying strategy are adopted respectively, which can effectively reduce the occurrence of cache fragments. The residence time of hot code in cache is prolonged as much as possible, and the hit rate of translation cache is improved. Finally, the instruction translation unit and translation cache component are designed and implemented by using Verilog HDL hardware description language. The main ports and functions are briefly described. The results of verification and analysis show that the instruction translation unit and the translation buffer unit designed in this paper can successfully map the X86 instruction set to the Alpha instruction set. The performance of instruction set mapping is improved by various optimization measures. Compared with the bytecode mechanism, the proposed two-stage decoding mechanism can achieve a maximum performance of 15.79%. The hit ratio of the proposed HTCM strategy is improved by 17.43% and 9.27% as compared with total emptying and FIFO.
【学位授予单位】：解放军信息工程大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332

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