基于动态局部可重构FPGA的容错技术研究

发布时间：2018-03-21 01:42

本文选题：Xilinx　切入点：FPGA　出处：《广西大学》2013年硕士论文　论文类型：学位论文

【摘要】：利用具有可重配置特性的现场可编辑门阵列(Field Programmable Gate Array,FPGA)可以在较短的时间内开发出稳定性高且安全系数大的电子产品。将FPGA的动态局部可重构技术用于实现容错系统,不仅提高了产品密度,缩短了开发周期,而且能保证系统的安全可靠,同时使硬件具备可重组性。本文研究的重点是利用动态局部可重构FPGA设计实现容错系统,主要工作包括：深入研究了FPGA原理和设计流程,探索各种动态重构系统设计方法,提出一种简化的动态自重构系统的设计方案。运用基于早期获取部分可重构(Early Access Partial Reconfiguration,EAPR)方法的原理及设计思想,在已存在的逻辑动态重构层次的基础上,进一步简化原有的设计流程,实现动态局部自重构。具体是依托Xilinx Virtex-4系列开发板,使用其配套工具,结合实例将所提出设计方法应用于容错系统,通过动态重构假定模块出错,建立可靠的模块化动态局部重构系统,证明所提方法的可行性及优越性。在实现局部动态重构的过程中,将整个容错系统作为研究对象,建立初始设计平台、划分静态与重构区域设定模块、分别并行设计各个模块、解决重构模块与可重构模块或与静态模块之间的通信问题、规划设计约束、产生比特流文件、合并组装。使用动态局部重构的方式完成故障恢复,简化恢复过程,最终完成整个系统,提高纠错速度。同时提出以内嵌的微处理器为核心的自重构方案,调度/管理芯片上的其他逻辑资源利用的是内部作为控制系统中心的硬核处理器,在可容错的通信实例中使用动态局部可重构技术并尽可能缩短重构时间。
[Abstract]:The field editable gate array Programmable Gate FPGA with reconfigurable characteristics can be used to develop electronic products with high stability and safety factor in a relatively short time. The dynamic local reconfigurable technique of FPGA is used to implement fault-tolerant system. It not only improves the product density, shortens the development cycle, but also ensures the safety and reliability of the system, and makes the hardware reconfigurable. The emphasis of this paper is to use dynamic local reconfigurable FPGA to implement fault-tolerant system. The main work includes: deeply studying the principle and design flow of FPGA, exploring various design methods of dynamic reconfigurable system. In this paper, a simplified design scheme of dynamic self-reconfiguration system is presented. The principle and design idea of early acquisition of early reconfigurable Access Partial reconfiguration are used. This paper further simplifies the original design flow and realizes dynamic local self-reconfiguration, which is based on Xilinx Virtex-4 series development board, using its matching tools, and applying the proposed design method to fault-tolerant system through dynamic refactoring, the module error is assumed by dynamic refactoring. A reliable modular dynamic local reconstruction system is established to prove the feasibility and superiority of the proposed method. In the process of realizing local dynamic reconstruction, the fault-tolerant system is taken as the research object and the initial design platform is established. Dividing static and reconfigurable region setting modules, designing each module in parallel, solving the communication problem between reconfigurable module and reconfigurable module or static module, planning and designing constraints, generating bitstream files. Merging and assembling. Using dynamic partial reconfiguration to complete the fault recovery, simplify the recovery process, finally complete the whole system, and improve the error correction speed. At the same time, a self-reconfiguration scheme with embedded microprocessor as the core is proposed. The other logical resources on the scheduling / management chip are the hardcore processor which is the center of the control system. The dynamic local reconfigurable technology is used in the fault-tolerant communication instance and the reconfiguration time is shortened as much as possible.
【学位授予单位】：广西大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP302.8

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