TMR故障注入与验证方法研究与实现

发布时间：2018-03-22 07:04

本文选题：三模冗余　切入点：故障注入　出处：《计算机测量与控制》2014年01期 　论文类型：期刊论文

【摘要】：从系统验证和FPGA物理原型验证两个方面,分析了TMR结构的注错方式及其验证方法;通过在TMR结构中嵌入注错逻辑,并将所有组TMR寄存器的注错控制信号统一命名,作为系统的输入,根据随机生成的注错信息,索引对应的TMR寄存器,可实现向对用户透明的任意TMR组中注错;将每组TMR寄存器的参考点和观测点引到设计的顶层统一命名,作为待测系统的输出,可适时观测对应TMR寄存器组的注错情况,分析故障电路的行为;为了解决调试机与FPGA板连接的引脚数受限的问题,特别设计了注错控制器和故障收集器;根据具体的注错情况,可编写对应的测试程序,验证设计的正确性,实验结果表明,SOC系统的错误故障率约占18.6%;为系统的可靠性评估提供了依据。
[Abstract]:From the two aspects of system verification and FPGA physical prototype verification, this paper analyzes the error-injection mode and verification method of TMR structure, by embedding the error-injection logic into the TMR structure, and naming the error-injection control signals of all groups of TMR registers. As the input of the system, according to the randomly generated error-annotating information and the corresponding TMR register, it can be realized to annotate errors in any TMR group that is transparent to the user, and the reference points and observation points of each group of TMR registers can be led to the top level of the design. As the output of the system to be tested, the error-injection situation corresponding to the TMR register group can be observed in time, and the behavior of the fault circuit can be analyzed, in order to solve the problem of the limited number of pins connected between the debugging machine and the FPGA board, the error injection controller and the fault collector are specially designed. According to the specific case of fault injection, the corresponding test program can be written to verify the correctness of the design. The experimental results show that the failure rate of SOC system is about 18.6, which provides the basis for the reliability evaluation of the system.
【作者单位】：西安微电子技术研究所;
【基金】：国家863计划项目(2011AA120201)
【分类号】：TN47;TP302.8

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