嵌入式系统中低功耗可重构Cache的研究与设计

发布时间：2018-03-23 01:06

本文选题：Cache　切入点：低功耗　出处：《湖南大学》2012年硕士论文　论文类型：学位论文

【摘要】：近年来，能耗已经成为嵌入式系统设计中人们关注的焦点，这主要是因为电池供电的便携式和移动式的嵌入式产品的广泛应用。高速缓冲存储器，即Cache，是为了解决存储器和CPU速度匹配而出现的。根据程序时间和空间局部性原理，在程序运行过程中，系统把部分数据从主存中调入到Cache，，从而CPU直接访问Cache，减少访问存储器的时间。因此Cache对计算机系统的性能有着重要的影响。同时，Cache消耗的能量占整个处理器功耗的大部分。因此，如何降低Cache的功耗有着重大的意义。本文详细的分析了国内外低功耗Cache的研究现状，在可重构Cache技术的基础上，提出了基于分支指令频率的动态可重构Cache（BRDRC）方案和基于指令时间数的动态可重构Cache（IC-DRC）方案。动态可重构Cache技术是在程序运行过程中根据程序的需求动态的调整Cache的结构，关闭Cache中闲置未用部分的能量消耗，从而在性能损失最小的情况下，有效地降低Cache功耗。 BRDRC算法根据分支指令频率监测程序段是否发生变化，并确定容量调整。在程序段内，状态机根据动态配置策略先对Cache的关联度进行调整，然后根据新配置下Cache的缺失率确定当前程序段Cache的最佳结构。与已有的算法相比，BRDRC算法不仅更有效地降低了Cache功耗，还大大减少了硬件开销。 IC-DRC算法则在BRDRC算法上进行改进，根据指令时间数监测程序段的变化，确定容量调整。在程序段内，状态机根据平均访问时间对Cache的访问进行预判，然后根据预判的结果确定当前程序段的Cache结构。预判机制的引入，不仅可以有效地避免不必要的重构，还能减少性能的损失。同时平均访问时间比缺失率能更好的反应性能的情况。实验结果表明，与BRDRC算法和已有算法相比，IC-DRC算法明显地改善了性能损失，进一步的降低了Cache功耗。
[Abstract]:In recent years, energy consumption has become the focus of attention in embedded system design, which is mainly due to the widespread use of battery-powered portable and mobile embedded products. In order to solve the problem of memory and CPU speed matching, according to the principle of program time and space localization, The system transfers part of the data from main memory to Cache. so CPU can access Cachedirectly and reduce the time of accessing memory. Therefore, Cache has an important effect on the performance of computer system. At the same time, the energy consumed by Cache accounts for the power consumption of the whole processor. Most of them. So, How to reduce the power consumption of Cache has great significance. In this paper, the research status of low-power Cache at home and abroad is analyzed in detail. On the basis of reconfigurable Cache technology, A dynamic reconfigurable Cache scheme based on branch instruction frequency and a dynamic reconfigurable Cache scheme based on instruction time number are proposed. The dynamic reconfigurable Cache technology is to dynamically adjust the structure of Cache according to the requirements of the program during the running of the program. The energy consumption of idle and unused parts of Cache is closed so that the power consumption of Cache is reduced effectively under the condition of minimum performance loss. The BRDRC algorithm monitors whether the program segment changes according to the branch instruction frequency, and determines the capacity adjustment. In the program segment, the state machine adjusts the correlation degree of Cache according to the dynamic configuration strategy. Then, according to the missing rate of Cache in the new configuration, the optimal structure of the current program segment Cache is determined. Compared with the existing algorithms, the proposed algorithm not only reduces the Cache power consumption more effectively, but also greatly reduces the hardware overhead. The IC-DRC algorithm is improved on the BRDRC algorithm, which monitors the program segment according to the instruction time and determines the capacity adjustment. In the program segment, the state machine prejudges the Cache access according to the average access time. Then the Cache structure of the current program segment is determined according to the results of the pre-judgment. The introduction of the pre-judgment mechanism can not only effectively avoid unnecessary refactoring. At the same time, the average access time is better than the missing rate. The experimental results show that compared with the BRDRC algorithm and the existing algorithm, the IC-DRC algorithm significantly improves the performance loss and further reduces the Cache power consumption.
【学位授予单位】：湖南大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332

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