片上网络开关分配的设计与分析

发布时间：2018-03-24 11:51

本文选题：片上网络　切入点：开关分配　出处：《国防科学技术大学》2014年硕士论文

【摘要】：随着片上所能集成处理器核数的不断增加,片上网络技术的重要性日渐明显,正逐渐成为影响片上多核系统性能的瓶颈。开关分配作为片上网络路由器中的关键部件,其性能对路由器以及整个片上网络的性能都会产生很大影响,已成为片上网络研究的热点。传统的开关分配方法基于长报文设计,而片上网络中多为短报文,传统的开关分配方法已不适应片上网络的需要。因此,如何针对片上网络短报文占优的特性,设计单周期可实现的、高效的开关分配方法,成为片上网络性能提高的关键。基于上述问题,本文将从以下四个方面展开研究:1.深入了解片上网络和开关分配方法的发展现状,对传统开关分配方法进行分析总结。深入研究片上网络报文传输的特性及其给开关分配方法设计带来的挑战,对已有的针对片上网络的高效开关分配方法进行分析总结,为设计高效的片上网络开关分配方法奠定基础。2.基于对片上网络高效开关分配方法的分析结果,提出将高效开关分配方法应用到典型低延迟路由器上来提高网络性能的方法。通过在低延迟路由器上实现高效的开关分配方法TS-Router等,极大降低了数据包传输的延迟,提高了网络吞吐率。3.针对片上网络输入端缓存结构路由器中存在的头阻塞效应,提出了一种新的基于动态调度的开关分配方法Reorder Buffer。该方法通过对缓存在路由器输入端的报文顺序进行调度,减少了开关分配阶段的冲突,提高了分配过程的匹配效率。使用Booksim模拟器进行性能分析的结果表明,Reorder Buffer可以有效降低网络延迟,提高吞吐率,其性能优于当前性能最好的开关分配方法TS-Router。4.基于降低片上网络延迟的需要,提出了将高阶拓扑应用到片上网络并结合高效开关分配策略以提高网络性能的方法。该方法将典型的高级拓扑Dragonfly布置在片上网络,并评测了在使用TS-Router等高效开关分配方法时的性能。实验证明,高阶拓扑可以有效降低片上网络延迟;在使用特定路由算法的情况下,高效开关分配方法可以进一步提高性能。综上所述,本文围绕“片上网络开关分配设计”这一目标,基于对片上网络特性的分析,优化设计了片上网络中的开关分配方法,并结合其他先进的片上网络技术使网络性能进一步提升。因此,本文解决了片上网络开关分配的一些实际问题,具有一定的工程价值和理论意义。
[Abstract]:With the increasing number of on-chip integrated processor cores, the importance of on-chip network technology is becoming more and more important, which is becoming a bottleneck affecting the performance of on-chip multi-core systems. Switch allocation is a key component in on-chip network routers. Its performance has a great impact on the performance of routers and the whole on-chip network, and has become a hot spot in the research of on-chip networks. The traditional switch allocation method is based on the design of long packets, while the on-chip network is mostly short packets. The traditional switch allocation method can not meet the needs of the on-chip network. Therefore, how to design a single cycle and efficient switch allocation method for the advantage of short packet on chip network. It is the key to improve the performance of on-chip network. Based on the above problems, this paper will carry out research on the following four aspects: 1.To understand the current situation of on-chip network and switch allocation methods. The traditional switch allocation method is analyzed and summarized. The characteristics of on-chip network message transmission and the challenges it brings to the design of switch assignment method are deeply studied, and the existing efficient switch allocation methods for on-chip network are analyzed and summarized. Laying a foundation for the design of efficient on-chip network switch allocation method. 2. Based on the analysis results of the on-chip network efficient switch allocation method, This paper presents a method to improve network performance by applying efficient switch allocation method to typical low-delay routers, which can greatly reduce the delay of packet transmission by implementing an efficient switch allocation method, TS-Router, on low-delay routers. The efficiency of network throughput is improved. 3. Aiming at the header blocking effect in the on-chip network input buffer structure router, In this paper, a new switch allocation method based on dynamic scheduling, Reorder buffer, is proposed, which reduces the conflict in the switch allocation phase by scheduling the sequence of packets cached at the input end of the router. The results of performance analysis using Booksim simulator show that reorder Buffer can effectively reduce network latency and increase throughput. Its performance is superior to the current best switch allocation method TS-Router.4.Based on the need to reduce the on-chip network delay, This paper presents a method to improve the network performance by applying high order topology to the on-chip network and combining the efficient switch allocation strategy. In this method, the typical high-level topology Dragonfly is arranged on the on-chip network. The performance of high-efficiency switch allocation methods such as TS-Router is evaluated. Experiments show that high-order topology can effectively reduce the on-chip network latency, and in the case of a specific routing algorithm, The efficient switch allocation method can further improve the performance. In summary, this paper optimizes the switch allocation method in the on-chip network based on the analysis of the characteristics of the on-chip network around the goal of "on-chip network switch allocation design". Combined with other advanced on-chip network technology, the network performance is further improved. Therefore, this paper solves some practical problems of on-chip network switch allocation, which has certain engineering value and theoretical significance.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP332

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