USB2.0控制器的IP核验证

发布时间：2018-03-25 08:28

本文选题：功能验证　切入点：断言　出处：《哈尔滨工业大学》2012年硕士论文

【摘要】：随着数字电路系统的功能日趋复杂，使电路或系统的功能验证难度逐渐增加。目前，在芯片开发全流程中，功能验证占用的资源占到全部开发资源约70%到90%左右，而RTL级的验证约占全部验证工作的50%。说明RTL级验证已经成为芯片设计过程中的重大瓶颈之一。以覆盖率驱动的验证方法是通过受约束的随机矢量激励输入到待验证模块（DUV），根据输出的结果来分析待验证模块的功能是否正确。采用这种方式的好处是可以较为方便的覆盖一个很大的验证空间，同时可以输入多次不同的激励，而逐渐覆盖到边缘情况。但是，上述方式在实际使用中依旧存在着缺陷，对仿真波形的分析及输出端口检查，短时间内不能准确定位设计错误之处，时间花费多，可观测性不强，不容易覆盖边缘。本文首先对现今主要的验证方法进行分析，阐述了以覆盖率为驱动的验证工作中遇见的困难，以及其必然的不足之处。针对复杂芯片验证中的困难，采用结合断言的以覆盖率驱动的验证方法。结合断言验证，可增强验证输出结果的可观测性，，及验证过程的可控性，从而弥补覆盖率驱动验证的不足。有利于较快的发现设计错误，缩短仿真测试周期，降低遗漏设计缺陷概率。之后本文对当下主流断言验证的语言进行分析，确定使用SVA作为验证工具。分析了使用SVA构建USB2.0控制器待验证环境的过程。本文采用的将两种验证方法相结合的方案，可有效提高验证工作的效率，从而缩减验证周期。最后，本文对验证输出结果进行了全面分析。对比结合断言的覆盖率驱动和只使用覆盖率为驱动两种验证方法的输出结果，可见前者节约了大量的验证时间。
[Abstract]:With the increasing complexity of the functions of digital circuit systems, the difficulty of functional verification of circuits or systems increases gradually. At present, in the whole process of chip development, functional verification occupies about 70% to 90% of the total development resources. The verification of RTL level accounts for about 50% of the whole verification work. It shows that RTL level verification has become one of the major bottlenecks in the chip design process. The verification method driven by coverage is to input the constrained random vector excitation to the module to be verified. According to the output results, the function of the module to be verified is analyzed. The advantage of this method is that it can be compared with that of the model. To easily cover a large verification space, At the same time, different excitation can be input several times, and gradually cover the edge case. However, the above method still has some defects in practical use, the analysis of the simulation waveform and the inspection of the output port, In a short period of time, it can not accurately locate the design errors, time is more expensive, observability is not strong, it is not easy to cover the edge. In this paper, the main verification methods are analyzed, and the difficulties encountered in the verification work driven by coverage are expounded, as well as the necessary shortcomings. In view of the difficulties in the verification of complex chips, Combined with assertion verification, the observability of the verification output and the controllability of the verification process can be enhanced. In order to make up for the lack of coverage driven verification, it is helpful to find design errors quickly, shorten the period of simulation test, and reduce the probability of missing design defects. Using SVA as the verification tool, this paper analyzes the process of using SVA to build the USB2.0 controller to be verified. The method of combining the two verification methods in this paper can effectively improve the efficiency of the verification work and thus reduce the verification period. Finally, this paper makes a comprehensive analysis of the verification output results. Comparing the results of the two verification methods, the coverage driven method combined with the assertion and only using coverage as the driving method, the former saves a lot of verification time.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332

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