NROM产品参考电流Iref分析和失效研究

发布时间：2018-03-28 11:22

本文选题：NROM　切入点：参考电流　出处：《复旦大学》2012年硕士论文

【摘要】：传统闪存(flash)技术利用浮栅(Floating Gate)存储电荷,根据多晶硅栅(poly)中是否有电荷储存,表示这个单元存储信息是“0”还是“1”。随着关键尺寸的不断微缩,传统浮栅产品逐渐无法满足更高节点制程的要求,于是近几年一种新型的闪存(flash)产品：电子陷阱闪存(charge-trapping flash,简称CTF)开始逐渐投入应用,这种产品利用电荷陷阱储存数据,可在一定的面积范围内具备较高的存储能力,能够缩小单元尺寸,并可满足需要内建高密度嵌入式记忆体的应用产品的需求。作为CTF的代表,氮化物只读存储器(NROM)技术具有很强的市场竞争力。由于其特殊结构,既可以应用于NAND Flash也可以应用于NOR Flash。本文分析了NROM的制备工艺流程,系统研究了其参考电流Iref及相关的失效模式和改进方法。 NROM Flash与成熟的逻辑器件生产工艺是兼容的,只需在其基础上加上形成Flash cell部分所需的ONO和相关离子注入的工艺,这样对整个工艺所需光罩(mask)的数量上,也要比FG Flash少4-5层,大大节省了光罩和相关工艺开发的成本。更为重要的是,传统的FG Flash遇到微缩的极限,而基于氮化硅俘获原理的NVM技术是目前最有希望的解决方向之一。在NROM产品的生产测试中,Iref是非常关键的参数,由于受很多因素影响,所以在生产过程中,也是最容易失效的参数。一般正常情况下,写入操作后的Iref,和其初始值有很强的相关性。分析表明,要改善Iref01失效,可以通过提高90nm MOS的电流Icell值进行改善,尽量将其控制在一个安全范围内。可以先从存储单元独有的ONO结构厚度,沟道长宽等的微调进行着手,这样也不容易影响到外围电路CMOS的参数。研究发现当Polyl CD减少时,由于设计时考虑的每一小块的间距一定,那么单元晶体管的多晶硅栅Poly长度的减小,势必导致晶体管之间的间隔距离增大。而BLPKT IMP注入到源漏拐弯处口袋型区域的小反型区的离子将显著变多,扩散区域明显变大。虽然晶体管的沟道长度L从～94nm微调至、92nm,仅缩短了2nm,但是随之单元晶体管之间的距离增大了2nm,BL PKT IMP离子注入的范围也变大了2nm。由于反型区的变大,它最终导致了Icell的降低,从而导致这次参考电流Iref的失效。后端工艺也同样会导致参考电流失效。论文分析的一个案例表明,由于后段工艺中的铜制程的氮化层的异常造成,由于氮化层没有完全阻挡铜,导致铜扩散到旁边的氧化层中,连线失效,电阻变大甚至无法导通电流,导致量取的原始参考电流非常低,从而导致失效。经过讨论,我们推导出了这次后端工艺导致的参考电流失效模型。
[Abstract]:Traditional flash memory (flash) technology uses floating gate to store charge, according to whether there is charge storage in polycrystalline silicon gate polyp, indicating whether the information stored in this cell is "0" or "1". As the key size shrinks, Traditional floating gate products can not meet the requirements of higher node process gradually, so in recent years, a new type of flash flash product: electronic trap flash memory charge-trapping flash (abbreviated as CTFF) has been gradually put into use, which uses charge trap to store data. It can have high storage capacity in a certain area range, can reduce the size of the unit, and can meet the needs of the application products which need high density embedded memory built in. As the representative of CTF, nitride read only memory (RAM) technology has strong market competitiveness. Because of its special structure, it can be used in both NAND Flash and NOR Flash. The reference current Iref and related failure modes and improvement methods are systematically studied. The NROM Flash is compatible with the mature logic device manufacturing process, simply by adding the ONO and related ion implantation processes needed to form the Flash cell part, so that there are 4-5 layers less than the FG Flash in terms of the number of light masks required for the entire process. It greatly saves the cost of light mask and related process development. More importantly, the traditional FG Flash meets the limit of microshrinkage, and the NVM technology based on the principle of silicon nitride capture is one of the most promising solutions. In the production test of NROM products, Iref is a very important parameter, because it is affected by many factors, it is also the most easily invalid parameter in the production process. The analysis shows that to improve the Iref01 failure, the current Icell value of 90nm MOS can be improved by increasing the current Icell value of 90nm MOS. As far as possible, we can control it within a safe range. We can start with the ONO structure thickness, channel length and width, which is unique to the memory cell, so it is not easy to affect the CMOS parameters of the peripheral circuit. It is found that when the Polyl CD is reduced, the length of the polysilicon gate Poly of the unit transistor decreases due to the fixed spacing of each small block considered in the design. The distance between transistors will increase, and BLPKT IMP will significantly increase the number of ions implanted into the small inversion region of the pocket area around the source and drain corners. The diffusion region is obviously larger. Although the channel length L of the transistor is reduced by only 2 nm from 92nm to 92nm, the distance between the transistors increases by 2nmL PKT IMP ion implantation. It eventually led to a decrease in Icell, which led to the failure of the reference current Iref. The back-end process also leads to the failure of the reference current. A case study in this paper shows that because of the abnormal nitriding layer in the copper process, the nitrided layer does not completely block copper, It causes copper to diffuse into the oxide layer next to it, and the wire fails, the resistance becomes larger and even the current cannot be switched on, which results in a very low original reference current, which results in a failure. The model of reference current failure caused by this backend process is derived.
【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333

【共引文献】