高性能X-DSP指令流水线部件设计实现与软硬件协同验证

发布时间：2018-03-28 14:07

本文选题：数字信号处理　切入点：流水线技术　出处：《国防科学技术大学》2014年硕士论文

【摘要】：X-DSP处理器是由国防科技大学微电子所自主研发的一款高性能64位浮点向量多核DSP芯片,40nm工艺下,实现主频1GHz的设计目标,采用VLIW结构,40/80位变长指令集,支持32/64位定点/浮点运算,最大可支持11条标/向量指令混合并行发射。本文以高性能X-DSP处理器的开发与研制为背景,深入分析流水线技术,设计实现了指令流水线上的指令派发与指令流控部件,并基于所提出的软硬件协同验证平台对系统级指令流水线的功能进行验证。本文主要的创新点与工作内容包括以下几点:1)详细分析X-DSP处理器内核结构、指令格式与流水线结构特征,进而提出指令流水线部件中指令派发与流控部件的设计需求;2)基于超长指令字(VLIW)结构,设计并实现可跨取指包边界派发指令的指令派发部件,支持L1P旁路取指与仿真调试部件(ET)对流水线的控制功能;3)深入分析X-DSP分支延迟槽特征,结合对调试仿真的支持,设计并实现指令流控部件,完成对指令流的控制作用;4)针对指令派发与指令流控部件的逻辑设计,在指令流水线系统级分别对其逻辑功能进行验证,并完成覆盖率分析与逻辑综合;5)分析传统FPGA原型验证的基本原理与不足之处,提出一种基于PLI接口的新型调试/验证方案:利用PLI接口实现C函数与Verilog的嵌套调用、采用数据共享机制实现不同进程间的通信。在软硬件协同支持下,对X-DSP的指令流水线进行验证实践,实验结果表明该方案使得在设计阶段便可对调试接口以及流水线功能进行更为充分的验证。
[Abstract]:The X-DSP processor is a high performance 64-bit floating-point vector multi-core DSP chip developed by the Institute of Microelectronics of the University of National Defense Science and Technology. Under the technology of 40nm, the design goal of the main frequency 1GHz is realized, and the 40 / 80 bit variable length instruction set is adopted in the VLIW structure. It supports 32 / 64 bit fixed-point / floating-point operation, and can support the mixed parallel transmission of 11 standard / vector instructions. In this paper, pipeline technology is deeply analyzed based on the development and research of high-performance X-DSP processor. Designed and implemented the instruction dispatch and instruction flow control unit on the instruction pipeline, Based on the proposed hardware / software co-verification platform, the function of the system-level instruction pipeline is verified. The main innovation and work contents of this paper include the following points: 1) the kernel architecture of X-DSP processor is analyzed in detail. The instruction format and pipeline structure feature, and then put forward the design requirement of instruction dispatch and flow control unit in the instruction pipeline parts. Based on the VLIW) structure, we design and implement the instruction dispatch parts that can distribute instructions across the boundary of taking the finger packet. The control function of pipeline by supporting L1P Bypass selection and Simulation debugging Unit (et) is used to analyze the characteristics of X-DSP branch delay slot in depth. Combined with the support of debugging simulation, the instruction flow control unit is designed and implemented. The logical design of instruction dispatch and instruction flow control unit is completed. The logic function of instruction pipeline is verified at the system level. The basic principles and shortcomings of traditional FPGA prototype verification are analyzed, and a new debugging / verification scheme based on PLI interface is proposed: C function and Verilog nesting call is realized by PLI interface. The data sharing mechanism is used to realize the communication between different processes. With the support of hardware and software, the instruction pipeline of X-DSP is verified. The experimental results show that the scheme can fully verify the debugging interface and pipeline function in the design stage.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP332

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