基于P沟道存储单元的高可靠性闪存设计

发布时间：2018-03-29 08:36

本文选题：Flash　切入点：可靠性　出处：《苏州大学》2016年硕士论文

【摘要】：Flash是一种广泛应用于SoC上的重要存储器,在高密度数据的存储和嵌入式系统中的应用不断增加。随着工艺的进步,晶体管特征尺寸降低到了十个纳米的数量级,随机掺杂扰动等带来的工艺偏差、阈值电压降低带来的高漏电流等也给Flash设计带来了极大的挑战。论文以Flash存储器工作的可靠性为研究重点,主要对Flash存储器的外围电路中的灵敏放大器电路、电荷泵电路、字线驱动电路和电平转换电路进行了优化设计,提高了外围电路模块的可靠性。基于标准CMOS工艺的8Mbits非易失性存储器。本文系统平台建立在Cadence Virtuoso之上,用Hspice进行了电路的功能模块仿真,而整体电路的仿真用的是Hsim软件,电路版图使用Laker进行绘制。本论文的主要内容和研究对象是:首先,本文对存储单元采用何种沟道的浮栅MOS管进行了对比分析,将P沟道浮栅MOS管和N沟道浮栅MOS管的可靠性做了对比,得出P沟通存储单元相对于N沟道存储单元在可靠性方面的优势,因此本文最终选择了P沟道浮栅MOS管作为存储单元。其次,本文研究了Flash存储器外围电路中的灵敏放大器电路、电荷泵电路、字线驱动电路和电平转换电路。对这几个外围电路的传统电路进行分析,找出各自存在的缺点,并据此设计出符合要求的电路,通过Hspice对设计出的电路进行仿真分析,所设计电路都达到了设计目标。另外,本文在最后一章节中首先简要介绍了版图的设计布局、布线规则,之后对本课题的IP版图设计进行了简要介绍。然后对存储器进行整体仿真并对编程、读取和片擦除的仿真波形图进行了重点分析。
[Abstract]:Flash is a kind of important memory widely used in SoC. It is widely used in high density data storage and embedded system. With the development of technology, the characteristic size of transistor has been reduced to ten nanometers. The process deviation caused by random doping disturbance and the high leakage current caused by the decrease of threshold voltage have also brought great challenges to the design of Flash. This paper focuses on the reliability of Flash memory. The sensitive amplifier circuit, charge pump circuit, word line drive circuit and level conversion circuit in the peripheral circuit of Flash memory are optimized. The reliability of the peripheral circuit module is improved. The 8Mbits non-volatile memory based on standard CMOS technology is built on the platform of Cadence Virtuoso. The function module of the circuit is simulated by Hspice, and the whole circuit is simulated by Hsim software. The main contents and research objects of this paper are as follows: firstly, this paper makes a comparative analysis of what kind of channel floating gate MOS is used in the memory cell. The reliability of P-channel floating gate MOS transistor and N-channel floating gate MOS transistor are compared, and the advantages of P communication memory cell compared with N-channel memory cell in reliability are obtained. In this paper, the P-channel floating gate MOS transistor is chosen as the memory cell. Secondly, the sensitive amplifier circuit and charge pump circuit in the peripheral circuit of Flash memory are studied. This paper analyzes the traditional circuits of these peripheral circuits, finds out their shortcomings, designs the circuits that meet the requirements, and simulates the designed circuits through Hspice. In addition, in the last chapter of this paper, the layout of the layout, routing rules, Then the IP layout design of this topic is briefly introduced. Then the whole simulation of memory is simulated and the simulation waveform of programming reading and chip erasing is analyzed emphatically.
【学位授予单位】：苏州大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TP333

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