高性能处理器存取关键技术的设计与优化

发布时间：2018-03-29 23:09

本文选题：高性能处理器　切入点：存取队列　出处：《上海交通大学》2013年硕士论文

【摘要】：随着半导体工艺和计算机体系结构的不断发展，高性能处理器的运行速度和存储器运行速度之间的差异变得愈加明显，成为制约处理器性能提升的因素之一。从指令执行的角度分析，解决存储墙问题就是提高存储指令的执行效率。论文以存取队列为研究突破口，对高性能处理器中的存取关键技术进行了研究和设计。本论文对高性能处理器中的队列设计和主要的优化方法进行研究，在载入指令重新执行和“存储脆弱窗”算法的基础上，提出新的队列设计方案，称为ESVW。新的设计充分利用载入和存储数据的局部性，进一步降低存储系统被访问的频率。基于相同的设计思路，论文将存取队列和分布式设计的思想引入阵列处理器设计，提出基于存取队列和分布式缓存的处理器架构，充分利用DSP阵列处理器中载入和存储数据的局部性，缓解非规则数据存取操作灵活性差的问题，使存储带宽不再成为性能提升的瓶颈。论文完成ESVW的RTL设计和逻辑综合，，并对性能、面积等参数进行分析。借助SimpleScalar仿真器和SPEC测试程序，证实ESVW可进一步降低指令访问存储系统的频率，相比于SVW使系统获得约2%的性能提升。论文完成DSP阵列处理器中主要模块的RTL设计、验证和逻辑综合。使用二维离散余弦变换，快速傅里叶变换和FIR滤波等常见算法对存取队列的性能进行评估。结果显示，使用存取队列设计前后，系统获得约5%的性能提升，芯片面积增加4.7%。
[Abstract]:With the development of semiconductor technology and computer architecture, the difference between the speed of high performance processor and the speed of memory becomes more and more obvious. From the perspective of instruction execution, the solution to the problem of storage wall is to improve the efficiency of the execution of storage instructions. The key technology of access in high performance processor is studied and designed. In this paper, queue design and main optimization methods in high performance processors are studied. A new queue design scheme is proposed on the basis of loading instruction reexecution and "memory fragile window" algorithm. The new design is called ESVW.The new design makes full use of the locality of loading and storing data, and further reduces the frequency of accessing storage system. Based on the same design idea, this paper introduces the idea of access queue and distributed design to array processor design. This paper proposes a processor architecture based on access queue and distributed cache, which makes full use of the locality of loading and storing data in DSP array processors, and alleviates the problem of poor flexibility of irregular data access operations. The storage bandwidth is no longer the bottleneck of performance improvement. In this paper, the RTL design and logic synthesis of ESVW are completed, and the parameters such as performance and area are analyzed. With the help of SimpleScalar simulator and SPEC test program, it is proved that ESVW can further reduce the frequency of instruction access to the storage system. Compared with SVW, the performance of the system is improved by about 2%. In this paper, the RTL design, verification and logic synthesis of the main modules of DSP array processor are completed. Some common algorithms such as fast Fourier transform and FIR filter are used to evaluate the performance of access queue. The results show that before and after the design of access queue, the performance of the system is improved by about 5%, and the chip area is increased by 4.7%.
【学位授予单位】：上海交通大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332

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