基于FPGA的RapidIO总线接口设计、验证与实现

发布时间：2018-03-31 08:03

本文选题：系统互连　切入点：串行RapidIO　出处：《西安电子科技大学》2013年硕士论文

【摘要】：随着嵌入式处理技术的飞速发展，互连技术成为了嵌入式系统整体性能提高的瓶颈。RapidIO作为一种基于交换网络的点对点总线，能够很好的满足嵌入式系统的需求。RapidIO作为系统内部互连技术，具有高性能、高可靠性、低引脚数和结构灵活等特点。4x模式的串行RapidIO(简称SRIO)是本论文的研究重点。本论文的研究工作主要有：首先对目前流行的总线技术作了介绍，然后具体分析了RapidIO体系结构：逻辑层、传输层、物理层。这种层次划分具有很大的灵活性，可在任意层增加新的事务类型而无需更改其他层规范。本文根据体系结构的划分，对每一层的操作进行了详细分析。其次对RapidIO系统架构进行了说明工作，紧接着对串行物理层模块的设计、BUFFER模块的设计和基于IP核的用户接口的设计工作进行了说明。接着对串行物理层主要的功能模块设计出了时序转移图，说明时序转移过程，然后对设计的各个功能模块进行仿真验证，，对时序正确性进行说明，在功能上实现串行物理层；对BUFFER模块的流量控制进行了设计，给出波形仿真图，说明了设计的流量控制机制符合应用要求；对用户接口模块进行了设计工作，给出时序逻辑图，说明各个信号的时序跳转情况，然后进行功能验证工作，将波形仿真图与时序图做时序分析，得出结论：设计满足功能需求。最后搭载硬件实现平台，对本地设备访问和远程设备访问的用户接口模块在FPGA中实现。通过查看时序图，输入输出数据的对比，实现其功能的正确性，并且通过串口打印其收发的结果。
[Abstract]:With the rapid development of embedded processing technology, interconnection technology has become the bottleneck of improving the overall performance of embedded system. RapidIO is a point-to-point bus based on switching network. RapidIO can satisfy the requirement of embedded system well. RapidIO is the interconnect technology of the system, which has high performance and high reliability. The characteristics of low pin number and flexible structure. 4x serial rapid IOs (SRIO) is the focus of this thesis. The main research work of this thesis is as follows:. This paper first introduces the popular bus technology, then analyzes the RapidIO architecture: logic layer, transport layer and physical layer. New transaction types can be added to any layer without changing other layer specifications. The operation of each layer is analyzed in detail according to the partition of the architecture. Secondly, the structure of RapidIO system is explained, then the design of serial physical layer module and the design of user interface based on IP core are described. Then the serial physical layer of the main functional modules designed timing transfer diagram to explain the timing transfer process, and then the design of each functional module simulation, timing correctness of the description, in the function of the serial physical layer; The flow control of BUFFER module is designed, the waveform simulation diagram is given, and the designed flow control mechanism meets the requirements of application, the user interface module is designed, and the timing logic diagram is given. The timing jump of each signal is explained, and then the function verification is carried out, and the waveform simulation diagram and timing diagram are analyzed, and the conclusion is drawn that the design meets the functional requirements. Finally, the user interface module for local device access and remote device access is implemented in FPGA on the hardware implementation platform. The correctness of the function is realized by viewing the timing diagram and comparing the input and output data. And print the result of its transceiver through serial port.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP336

【参考文献】