SATA控制器的设计与FPGA验证

发布时间：2018-04-01 10:33

本文选题：串行高技术附件　切入点：高速串行收发器　出处：《太原理工大学》2013年硕士论文

【摘要】：随着集成电路性能的提高和网络技术的发展,数据规模空前膨胀,海量存储逐渐成为研究的重要课题。以计算机的硬盘为例,处理器的工作频率不断加快,并行接口(PATA)的信号之间干扰日益加剧,无法再满足时代的需要。串行传输应运而生,Serial ATA接口管脚少,传输速率快,设置多重数据纠错模式,支持热插拔特性,刚一出世便成为硬盘存储业的新宠。但该产品的关键技术大都集中在国外的垄断公司手中,国内主要对其分析修改,二次开发。鉴于SATA控制器市场空白,本文以此为切入点,设计面向FPGA的SATA主机控制器,旨在快捷便利地存储数据。 SATA标准为国外发布的协议,本文详细剖析了SATA1.0版本,深刻理解串行传输的层次架构,自上而下为命令层、传输层、链路层和物理层。设计采用FPGA自顶向下的模块化理念,以协议内容为框架,最大限度地发挥FPGA并行优势,命令层由FPGA的嵌入式处理器MicroBlaze来实现,主要完成硬盘的参数配置和读写命令。下面三层为设计重点,中间传输层和链路层主要完成帧的封装,帧的发送、暂停、结束控制,帧的解析和校验。按功能分为控制模块和数据通路,前者用VHDL描述为多个状态机协同控制实现,后者调用存储IP核FIFO保存数据,利用CRC和扰码校验双重数据纠错。最底层物理层包括高速串行收发器、OOB信号控制模块和速率协调模块。高速串行收发器对应协议中的模拟前端,可根据需求灵活配置8B/10B编解码,串并转换,COMMA字符检测,时钟修正,预加重和线性均衡等选项。OOB控制模块和速率协调模块能够自动识别硬盘的传输速率,实现了1.5Gbps/3.0Gbps自动切换的串行传输通路。整个设计使用Xilinx公司的ISE软件完成,各个模块附有仿真图和结果分析。系统验证采用Virtex-5开发板,把SATA控制器封装成IP核挂在PLB总线上,由处理器MicroBlaze设置硬盘命令,通过PLB,总线调配SATA控制器IP核对硬盘进行读写测试,结果符合协议要求。整个SATA控制器在FPGA上实现,集成度强、可移植性高,具有很好的工程和市场价值,在计算机存储领域具有重要意义。
[Abstract]:With the improvement of the performance of integrated circuits and the development of network technology, the data scale is expanding unprecedentedly. Mass storage is becoming an important research topic. Taking the hard disk of the computer as an example, the working frequency of the processor is speeding up. The interference between parallel interface (PATAA) signals is becoming more and more serious, which can no longer meet the needs of the times. Serial ATA interface has fewer pins, faster transmission rate, set up multiple data error correction mode, and support hot-plug characteristics. As soon as it was born, it became a new favorite of hard disk storage industry. However, the key technology of this product is mostly concentrated in the hands of foreign monopoly companies, and it is mainly analyzed and modified in our country. In view of the blank market of SATA controller, this paper takes this as the starting point. A SATA host controller for FPGA is designed to store data quickly and conveniently. The SATA standard is a protocol published abroad. This paper analyzes the SATA1.0 version in detail, deeply understands the hierarchical architecture of serial transmission, from top to bottom for command layer, transport layer, link layer and physical layer. The design adopts the idea of FPGA top-down modularization. Taking the protocol content as the frame, taking the FPGA parallel advantage to the maximum extent, the command layer is realized by the embedded processor MicroBlaze of FPGA, which mainly completes the parameter configuration of the hard disk and the command of reading and writing. The following three layers are the key points of the design. The intermediate transport layer and link layer mainly complete frame encapsulation, frame transmission, pause, end control, frame resolution and verification. The latter calls to store IP core FIFO to save data, uses CRC and scrambling code to check dual data error correction. The bottom layer of physical layer includes high speed serial transceiver OOB signal control module and rate coordination module. 8B/10B codec, serial-parallel conversion, clock correction, preweighting and linear equalization options. OOB control module and rate coordination module can automatically identify the transmission rate of hard disk. The serial transmission path of 1.5Gbps/3.0Gbps automatic switching is realized. The whole design is completed by ISE software of Xilinx Company, each module is accompanied by simulation diagram and result analysis. System verification adopts Virtex-5 development board, encapsulates the SATA controller into IP core and hangs on PLB bus, and the processor MicroBlaze sets the hard disk command. The whole SATA controller is implemented on FPGA with strong integration, high portability and good engineering and market value. It is of great significance in the field of computer storage.
【学位授予单位】：太原理工大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332;TN791

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