一种PLB-Wishbone的SoC总线桥接器的设计与实现

发布时间：2018-04-03 11:24

本文选题：SoC　切入点：PLB总线　出处：《西安电子科技大学》2013年硕士论文

【摘要】：随着集成电路的高速发展，，SoC（System on Chip）技术已经成为当今重要的发展方向。特别是基于各种IP核，可重用的SoC设计方法的出现，使得总线接口设计技术在高效且具有良好扩展性和兼容性的总线平台上显得意义非凡。总线及其接口技术决定了整个SoC的效率，效率不够高从根本上会削弱系统的性能，同时复杂的结构占用了本来大量有限的片上系统资源。所以，总线的选择对于SoC来讲至关重要，通过对当今流行的CoreConnect总线，AMBA总线，Wishbone总线以及OCP总线之间的比较，了解所需总线的特征，设计出适用的桥接器。 SoC芯片内各个IP模块通过片内高速总线进行互连，目前多种SoC总线协议的并存，使得IP核之间的复用变得困难。本文采用Verilog HDL设计实现一种高效的SoC总线协议桥接器，通过Wishbone从设备可与PLB总线有效结合，从而实现高速PLB总线到可自定义仲裁方式的Wishbone总线之间的协议标准转换，从而使PLB总线和Wishbone总线IP核的可复用性得到提高。在本文设计中，通过对FIFO的读、写保持了桥接器数据读写的一致，同时为实现时序的同步采用了异步电路握手控制方式。尽管Xilinx公司在其EDK设计工具中对于较为复杂的PLB总线，利用其向导工具生成一套专门为用户服务的接口模块，但它还存在一定的局限性，比如结构复杂、效率低下、片上系统资源占用较多等。因此对于研发自主知识产权的核心技术以及应用开发这方面的工作很有必要。本文针对PLB总线与Wishbone总线的互连接口如何实现读写，以及如何解决跨时钟域等问题，提出了设计方案，采用VerilogHDL进行设计并用Modelsim进行了仿真验证，得到的结果是该桥接器能够正确运行在系统中且能访问其他片上资源，同时使设计功能得到实现。
[Abstract]:With the rapid development of integrated circuits, SoCon system on Chip technology has become an important direction of development.Especially, the emergence of reusable SoC design method based on various IP cores makes the bus interface design technology very significant on the bus platform with high efficiency and good extensibility and compatibility.Bus and its interface technology determine the efficiency of the whole SoC, which can weaken the performance of the system fundamentally, and the complex structure takes up a large number of limited on-chip system resources.Therefore, the choice of bus is very important for SoC. By comparing the popular CoreConnect bus, Wishbone bus and OCP bus, we can find out the characteristics of the required bus and design a suitable bridge.Each IP module in SoC chip is interlinked by high speed bus. At present, the coexistence of various SoC bus protocols makes it difficult to reuse IP cores.In this paper, Verilog HDL is used to design and implement an efficient SoC bus protocol bridge, which can be effectively combined with PLB bus through Wishbone, so that the protocol standard conversion between high speed PLB bus and Wishbone bus with custom arbitration mode can be realized.Thus, the reusability of PLB bus and Wishbone bus IP core is improved.In the design of this paper, by reading the FIFO, the writer keeps the same data reading and writing of the bridge. At the same time, the asynchronous circuit handshake control mode is used to realize the timing synchronism.Although Xilinx used its wizard tools to generate a set of interface modules for the more complex PLB bus in its EDK design tools, it still has some limitations, such as complex structure and low efficiency.On-chip system resources occupy more and so on.Therefore, it is necessary to research and develop the core technology and application of intellectual property rights.In this paper, aiming at how to realize the interface between PLB bus and Wishbone bus, how to read and write, and how to solve the problem of cross-clock domain, this paper proposes a design scheme, which is designed by VerilogHDL and simulated by Modelsim.The result is that the bridge can run correctly in the system and can access other on-chip resources, at the same time, the design function can be realized.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP336;TN47

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