结合结构级和门级的多核处理器功耗评估方法

发布时间：2018-04-04 01:13

本文选题：片上多核处理器　切入点：功耗评估　出处：《湖南大学》2013年硕士论文

【摘要】：功耗评估是功耗优化的基础。近年来，功耗已经成为处理器设计的重要限制因素，更凸显了功耗评估在处理器设计中的作用。单核处理器时代已经过去，片上多核处理器不可阻挡地成为当今处理器的主流。如何为片上多核处理器建立准确的功耗模型成为学术界研究的热点课题之一。根据芯片设计的不同阶段，功耗评估方法分为结构级、寄存器传输级、门级、晶体管级四种类型，其中结构级和门级功耗评估方法由于各自鲜明的特点，获得了最多的关注。然而，，随着处理器设计方法的转变和制造工艺的进步，使得原有的结构级功耗评估方法已经无法准确地估算处理器的功耗；而门级功耗评估方法由于需要具体的电路信息，不能在设计初期对处理器的功耗做出及时的评估和反馈。针对上述不足，本文提出了一种结合结构级和门级的功耗评估方法。该方法既继承了结构级功耗评估方法的速度，又能改善其精度，同时，还具有一定的灵活性。具体研究工作如下：首先，分别在电路级和体系结构级划分多核处理器。电路级划分的依据是处理器功能电路体现出来的不同功耗特点，电路类型划分为：组合逻辑，时序逻辑和互连线，为每种类型选用合适的功耗建模方法，即门级功耗分析方法或者结构级功耗分析方法；体系结构级划分的依据是模块的功能，将处理器核心，片上网络，片上高速缓存和时钟网络划分为模块的组合，并将这些模块映射到上述电路类型中的一种。然后，对于适合用门级功耗分析方法测算功耗的基本模块，依照集成电路的设计流程，从RTL代码的设计开始，经过综合、布局、布线等一系列流程，得到门级网表，由门级网表分析得到基本模块的门级功耗值。RTL代码的设计考虑了基本模块的体系结构参数和结构设计，尽可能地涵盖基本模块所能出现的各种情况，并将这些功耗值制成功耗查找表的形式。最后，修改结构级功耗模拟器McPAT，使本文中的功耗查找表集成其中；配置Gem5使其模拟目标处理器的运行；修改性能模拟器Gem5，使其能记录程序运行时各模块的访问次数。实验结果表明，与结构级功耗评估工具McPAT相比，本文的功耗评估方法可以更准确地评估功耗。
[Abstract]:Power evaluation is the basis of power optimization.In recent years, power consumption has become an important limiting factor in processor design, which highlights the role of power evaluation in processor design.The era of single-core processors has passed and multi-core processors on-chip have become the mainstream of processors.How to build an accurate power model for multi-core processors on-chip has become one of the hot topics in academic research.According to the different stages of chip design, power evaluation methods are divided into four types: structure level, register transfer level, gate level and transistor level.However, with the change of processor design method and the progress of manufacturing technology, it is impossible to estimate the power consumption of the processor in the original structure level power evaluation method, and the gate level power evaluation method requires specific circuit information.The power consumption of the processor can not be evaluated and feedback in time at the beginning of the design.In order to solve these problems, this paper proposes a power evaluation method combining structure level and gate level.This method not only inherits the speed of the structure level power evaluation method, but also improves its accuracy. At the same time, it has some flexibility.The specific studies are as follows:First, multi-core processors are divided at circuit level and architecture level, respectively.The circuit level partition is based on the different power consumption characteristics of the processor functional circuit. The circuit types are divided into combinational logic, sequential logic and interconnect lines, and a suitable power modeling method is selected for each type.That is, gate power analysis method or structure-level power analysis method, architecture level partition is based on the function of the module, the processor core, on-chip network, on-chip cache and clock network are divided into modules.These modules are mapped to one of the above circuit types.Then, for the basic module which is suitable for power analysis at gate level, according to the design flow of integrated circuit, starting with the design of RTL code, after a series of processes such as synthesis, layout, wiring and so on, the gate level network table is obtained.The gate power consumption value. RTL code of the basic module is obtained by analyzing the gate network table. The architecture parameters and structure design of the basic module are considered, and the various situations that can occur in the basic module are covered as much as possible.These power values are made into a power look-up table.Finally, the structure level power simulator McPATs are modified to integrate the power look-up table in this paper; the Gem5 is configured to simulate the operation of the target processor; and the performance simulator, Gem5, is modified to record the number of visits to each module while the program is running.The experimental results show that the proposed method is more accurate than the structure level power evaluation tool McPAT.
【学位授予单位】：湖南大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332

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