基于PCI Express总线的高速数据传输系统的设计与实现

发布时间：2018-04-04 19:13

本文选题：FPGA　切入点：PCI　出处：《北京邮电大学》2013年硕士论文

【摘要】：随着计算机应用对带宽需求的日益增长,PCI Express总线协议作为PCI-SIG规范并标准化的第三代高性能的IO总线技术,拥有点到点的串行数据高速传输等诸多优势,成为未来总线技术的发展趋势。高速数据传输系统是指上位机服务器和下位机硬件平台通过PCI Express桥芯片实现高速通信的DNS防火墙设备。本课题首先对PCI Express总线协议作了基本论述,然后对DNS防火墙系统从硬件、软件和应用程序三方面作了概述。最后重点对PCI Express桥芯片的设计作了详细阐述。课题采用Altera芯片厂商的Cyclon IV GX系列的FPGA实现,该FPGA内嵌了PCIe的IP硬核,该硬核实现了PCI Express总线协议的事务层、数据链路层和物理层的功能,所以课题只需要对PCI Express协议的应用层进行逻辑设计。应用层逻辑设计实现了单包读写(PIO)通路和DMA读写通路两种数据传输方式。课题首先对高速数据传输系统进行需求分析,然后给出了基于FPGA的PCI Express桥芯片的设计方案,包括逻辑设计框图、接口说明及总线时序等。在此基础上,采用Verilog HDL硬件描述语言完成了应用层的RTL代码设计,实现了PIO通路和DMA通路功能。最后对高速数据传输系统进行系统级仿真验证,测试结果表明：PCIExpress桥芯片采用X1通道,DMA通路的读数据传输速率达到168MB/S,写数据传输速率达到172MB/S,满足上位机服务器和下位机硬件平台进行高速通信的速率要求。此外,还根据需求扩展到X4通道获得更高的传输速率。目前,DNS防火墙设备成功在线上部署,并得到广泛应用。
[Abstract]:With the increasing demand for bandwidth in computer applications, the PCI Express bus protocol, as the third generation of high-performance IO bus technology with PCI-SIG standardization and standardization, has many advantages such as point-to-point serial data high-speed transmission and so on. It has become the development trend of the future bus technology.
High speed data transmission system is a PC server and client hardware platform to realize the DNS firewall equipment high speed communication through the PCI Express bridge chip. This paper describes the basic principle of PCI Express bus protocol, and then the DNS firewall system from hardware, software and application in three aspects are summarized in detail on the design. PCI Express bridge chip. The last major project uses the Altera Cyclon GX series IV chip manufacturers to achieve the FPGA, the FPGA embedded PCIe IP core, the core to achieve PCI Express bus transaction layer, data link layer and physical layer, so we only need to PCI the application layer of Express protocol logic design. Application layer logic design to achieve a single package to read and write (PIO) pathway and DMA pathway to read and write two kinds of data transmission.
Firstly, the demand analysis of the high speed data transmission system, and then gives the design scheme of PCI Express bridge chip based on FPGA, including the logic diagram design, interface description and bus timing. On this basis, using Verilog HDL hardware description language to complete the RTL code design application layer, realizes the PIO pathway and DMA pathway function finally. The system simulation results of high-speed data transmission system, the test results show that the PCIExpress bridge chip X1 read channel, data transmission rate of the DMA pathway to 168MB/S, write the data transmission rate of 172MB/S, to meet the PC server and client hardware platform for high-speed communication. In addition, according to the demand expansion to X4 channel to obtain higher transmission rate. At present, the successful deployment of DNS firewall equipment online, and widely used.

【学位授予单位】：北京邮电大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP336

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