动态二进制翻译建模及其并行化研究

发布时间：2018-04-08 13:24

本文选题：动态二进制翻译　切入点：间接分支　出处：《中国科学技术大学》2013年博士论文

【摘要】：随着国产处理器的发展,特别是国产多核处理器的发展,解决软件高效移植的问题已经成为新处理器能否占领市场的关键因素。二进制代码的兼容性是限制软件移植关键问题,也是限制新的体系结构发展的重要障碍。动态二进制翻译(Dynamic Binary Translation, DBT)技术作为一种跨平台的动态编译技术,为通过软件的方法解决不同体系结构之间的二进制代码兼容性提供了可能,也为程序动态优化和计算机虚拟化提供了新的方向。由于现代硬件体系结构的高度复杂性,不同的体系结构之间存在着巨大的差异。动态二进制翻译技术为了弥补这些硬件上差异,需要耗费大量的额外开销进行模拟,直接导致了动态二进制翻译系统的性能远远低于本地程序的性能,阻碍了该技术的广泛应用。如何提高动态二进制翻译系统的性能是该领域的核心研究问题。由于多核平台所具有的丰富计算资源,对传统单线程动态二进制翻译系统进行并行化是当前研究的热点问题。本文在对龙芯处理器的动态二进制翻译系统研究工作中,基于大量相关动态运行时系统的分析,为动态二进制翻译系统的整个执行过程构建出“翻译-执行-查找”的动态模型。通过该模型,也就可以把动态二进制翻译系统和类似的运行时系统简洁地划分为翻译模块,执行模块和查找模块。本文的研究内容和优化方法也围绕着这三个模块,主要研究内容包括以下几个方面： 1.归纳出动态二进制翻译系统的“翻译-执行-查找”模型：本文在对大量的运行时系统分析的基础上,归纳出动态二进制翻译系统执行过程中的“翻译-执行-查找”的动态模型。把动态二进制翻译系划分为翻译模块,执行模块和查找模块,为进一步研究工作提供准确的优化方向。 2.设计出一种带私有缓存的间接分支目标地址查找算法：在查找模块中,间接分支指令的处理是动态二进制翻译系统中的性能瓶颈,本文通过对间接分支目标地址的局部性分析,提出利用私有缓存快速查找间接分支目标地址的算法,有效减少了间接分支引起的上下文切换次数。 3.改进了动态二进制多线程翻译模型：在翻译模块中,本文详细分析和对比了已有的多线程翻译模型优缺点,提出了基于栈模式的预测算法并利用等待队列来管理多个翻译线程,提出内存拷贝的方法改善分布式代码缓存的局部性。利用这些优化方法改善了多线程翻译模型的性能。 4.提出了全寄存器直接映射方法：在执行模块中,寄存器的模拟器方式对于翻译代码膨胀率和被翻译程序的性能有着至关重要的影响。本文综合了基于内存和直接映射的寄存器模拟方法,提出了在动态二进制翻译机制中使用全部寄存器直接映射方法,并在此基础上,进行大量的中间代码的翻译规则简化,提高了后端代码的翻译质量。 5.设计和实现基于龙芯平台的原子指令模拟方法：在执行模块中,为了实现对于独立计算单元的线程级并行化,本文基于已有的并行多核模拟器系统,在龙芯平台上设计并实现了线程级并行的多核模拟器。针对并行模拟器中内存模拟问题和原子指令模拟问题,提出了基于龙芯体系结构的解决方法。
[Abstract]:With the rapid development of the domestic processors, especially the domestic development of multi-core processors, solve the efficient software transplantation has become a key factor to occupy the market. The new processor binary code compatibility is the key problem restricting transplantation software, an important barrier also restricts the development of new architecture. Dynamic binary translation (Dynamic Binary, Translation, DBT) as a dynamic cross platform compiler technology, provides the possibility to solve the binary code compatibility between different system structure by software method, also state optimization and computer virtualization provides a new direction for the program.
Due to the high complexity of modern hardware architecture, there are great differences between different architectures. Dynamic binary translation technology in order to compensate for these differences requires additional hardware overhead, a lot of simulation, led directly to the performance of dynamic binary translation system is much lower than the performance of local procedures, hinder the wide application of the technology. How to improve the performance of dynamic binary translation system is the core issue in this field. Because the multi-core platform has rich computing resources, parallel to the traditional single thread dynamic binary translation system is a hot topic of current research.
Based on the research of dynamic binary translation system on the Godson processor in the analysis of a large number of relevant dynamic runtime system based on the entire implementation process for dynamic binary translation system to construct a dynamic model of translation - Implementation - Search ". Through this model, it can make the dynamic binary translation system and similar operation the system is divided into simple translation module, execution module and search module. The research content and the optimization method in this paper is focus on these three modules, the main contents include the following aspects:
1. summed up the dynamic binary translation system "translation do find" model: Based on a large number of runtime system on the basis of the analysis, summed up the dynamic binary translation system in the implementation of the "translation - Execution - Dynamic Model Search". The dynamic binary translation system is divided into translation module, execution module and a search module provides accurate optimization direction for further research work.
2. design an indirect branch target address lookup algorithm with private cache: the search module, processing of indirect branch instruction is the performance bottleneck in dynamic binary translation system, through the analysis of local indirect branch target address, proposed to use private cache to quickly find the indirect branch target address algorithm, effectively reduce the the number of context switches caused by indirect branches.
3. improved dynamic binary translation model: multi thread in the translation module, this paper analyzes and compares the advantages and disadvantages of existing multi thread translation model, prediction algorithm is proposed based on stack model and use the queue to manage multiple threads, local memory copy method is proposed to improve the utilization of these distributed code caching. The optimization method can improve the performance of multi thread translation model.
4. proposed full register direct mapping method: in the implementation of the module, the register simulator has a critical influence on the translation of code expansion efficiency and performance of the translated program. In this paper a comprehensive simulation method and direct memory mapped register based on the proposed dynamic binary translation mechanism used in all registers directly mapping method, and on this basis, a large number of intermediate code translation rules simplify, improve the translation quality of the backend code.
The simulation method of Loongson platform based on the design and implementation of 5. atomic instructions: in the implementation of the module, in order to achieve the independent thread level parallel computing unit, the parallel simulator system based on the design and implementation of multi-core simulator thread level parallelism on Loongson platform. The parallel simulator in memory simulation the problem and the atomic instruction simulation problems, and puts forward the solution of Loongson based architecture.

【学位授予单位】：中国科学技术大学
【学位级别】：博士
【学位授予年份】：2013
【分类号】：TP332;TP391.2

【引证文献】