DSP-DX取指派发部件的设计优化与实现

发布时间：2018-04-13 01:08

本文选题：跨边界派发 + 混合指令　；参考：《国防科学技术大学》2013年硕士论文

【摘要】：DSP-DX CPU是一款支持定点和浮点运算的新一代DSP,采用支持8流出的VLIW结构。传统VLIW体系结构的DSP具有指令代码体积大,存取效率低的问题。为解决这些问题,DSP-DX CPU采用了16位/32位混合指令集和跨边界派发技术。这些技术的逻辑结构在取指部件的指令接收站(PR站)和派发部件的指令派发站(DP站)实现。由此增加了取指派发部件实现的复杂度和时延。在40nm工艺和SS的情况下需要对取指派发部件进行逻辑结构和时序优化以保证设计目标的实现。按照DSP-DX CPU的设计要求,本文主要完成如下的工作 1.为压缩代码体积和提高执行效率,取指派发部件采用跨边界派发技术和16位/32位混合指令技术,对派发部件的结构进行设计和验证,特别对并行位ID和分支ID产生电路及指令派发控制位产生等电路进行了逻辑设计,提高了指令执行并行度并验证了其功能正确性。 2.用微体系结构优化的方法完成关键模块的时序优化,利用DC综合工具对取指派发部件进行综合优化,找出关键路径,确定各个模块的优化实现策略,调整了关键路径上的逻辑结构,优化结果表明消除了关键路径延时,达到总体设计目标要求。 3.采用手工半定制设计的方法完成了取指派发部件物理设计,并通过DRC和LVS检查,达到了比较好的时序优化效果。
[Abstract]:DSP-DX CPU is a new generation of DSP which supports fixed-point and floating-point operations.The traditional VLIW architecture of DSP has the problems of large size of instruction code and low access efficiency.To solve these problems, DSP-DX CPU uses 16-bit / 32-bit hybrid instruction set and cross-border distribution technology.The logical structure of these techniques is realized at the instruction receiving station (PR station) and the instruction dispatch station (DP station).Thus, the complexity and delay of the implementation of the fetch and dispatch components are increased.In the case of 40nm process and SS, it is necessary to optimize the logical structure and timing of the wire-out parts to ensure the realization of the design objectives.According to the design requirements of DSP-DX CPU, this paper mainly completes the following work1.In order to compress the size of code and improve the efficiency of execution, the distributed parts are designed and verified by using cross-boundary dispatch technology and 16-bit / 32-bit hybrid instruction technology.In particular, the parallel bit ID and branch ID generation circuits and the instruction dispatch control bit generation circuits are designed, which improves the parallelism of instruction execution and verifies the correctness of its function.2.The timing optimization of the key modules is accomplished by the method of microarchitecture optimization, and the key path is found out by using the DC synthesis tool to optimize the finger picking and distributing parts, and the optimal realization strategy of each module is determined.The logic structure of the critical path is adjusted and the optimization results show that the delay of the critical path is eliminated and the overall design goal is achieved.3.The manual semi-custom design method is used to complete the physical design of the finger picking and distributing parts, and through the DRC and LVS checks, a better timing optimization effect is achieved.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332.2

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