容错处理器阵列的快速重构算法研究

发布时间：2018-04-14 12:23

本文选题：处理器阵列 + 容错技术　；参考：《天津工业大学》2017年硕士论文

【摘要】：目前超大规模集成电路技术把大量的处理器单元集成到单一芯片上,从而使用多处理器系统执行很多大规模的并行任务。随着VLSI阵列密度的增加,系统运行期间PEs发生故障的概率也在增加。这些发生故障的PEs会破坏已有的网络通讯结构,为了保证系统的稳定性和可靠性,获得无故障逻辑阵列的重构技术成为有意义的研究课题。本文通过研究降阶策略,针对快速重构无故障逻辑阵列的问题,研究了处理器阵列上的快速重构,具体工作内容如下:第一,文中提出了一个最短路径段优先扩展的逻辑列重构算法,该算法优先扩展最有可能生成最优逻辑列的路径段,即总是选择当前长连接数最少的路径段进行扩展,从而确保生成的逻辑列为最优逻辑列。由于最优逻辑列上的路径段往往可以被率先扩展到终点,因此算法能够更加快速地构造出整个最优逻辑列,并不需要计算相关区域所有PEs的路径信息,从而克服了现有的动态规划算法需要计算所有无故障PEs的弱点。第二,在构建好一个最优逻辑整列后,处理器还是可能随时出现故障,本文针对原有的逻辑阵列中发生实时故障下的阵列重构问题,研究如何在实时故障下快速重构一个尽可能大的新逻辑阵列。原有的处理方案在解决此问题时,一般都会推翻原有的逻辑阵列结构,在整个主阵列的基础上重新构建最大的逻辑阵列。然而通过研究发现,在某些情况下并不需要对整个主阵列进行重构,就可得到一个相对大的逻辑阵列。因此,文中设计了一个有效的预处理技术,可在局部区域产生一条最优逻辑列来替换原有的包含实时故障PE的逻辑列。该技术并不需要对所有的逻辑列进行构建,因此可以快速的生成一个相对大的逻辑阵列,从而减少通讯延迟,节省网络的资源消耗。
[Abstract]:At present, VLSI technology integrates a large number of processor units into a single chip, so that multiprocessor systems are used to perform many large-scale parallel tasks.With the increase of VLSI array density, the probability of PEs failure increases during system operation.These malfunctioning PEs will destroy the existing network communication structure. In order to ensure the stability and reliability of the system, obtaining the fault-free logic array reconstruction technology has become a meaningful research topic.In this paper, order reduction strategy is studied to solve the problem of fast reconstruction of fault-free logic array, and the fast reconfiguration on processor array is studied. The main work is as follows: first,In this paper, a logic sequence reconstruction algorithm with the shortest path segment first extended is proposed. The algorithm gives priority to the path segment that is most likely to generate the optimal logical sequence, that is, the path segment with the least number of connections is always selected for expansion.This ensures that the generated logic is an optimal logical column.Because the path segment on the optimal logic sequence can be extended to the end point first, the algorithm can construct the entire optimal logic sequence more quickly, without the need to calculate the path information of all the PEs in the related region.Therefore, it overcomes the weakness of the existing dynamic programming algorithm which needs to compute all the fault-free PEs.Second, after constructing an optimal logic sequence, the processor may fail at any time. This paper aims at the problem of array reconfiguration under the real-time fault in the original logic array.This paper studies how to reconstruct a new logic array as large as possible in real time fault.When the original processing scheme solves this problem, the original logical array structure will be overturned, and the largest logical array will be reconstructed on the basis of the whole main array.However, it is found that in some cases, a relatively large logical array can be obtained without the need to reconstruct the entire main array.Therefore, an effective preprocessing technique is designed to generate an optimal logic sequence in the local region to replace the original logic sequence containing the real time fault PE.This technique does not need to build all the logical columns, so it can quickly generate a relatively large logical array, thus reducing communication delay and saving network resource consumption.
【学位授予单位】：天津工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP332

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