分块内存的数据分布优化

发布时间：2018-04-15 18:53

本文选题：分块内存 + 地址生成单元　；参考：《小型微型计算机系统》2015年04期

【摘要】：为了提高访存效率,提供可以与计算流水线并行执行的多个独立的访存流水线,魂芯DSP片上存储器设计时采用分块内存结构,并在核内提供多个独立的地址生成单元用于访存操作.针对分块内存的结构特点,编译器对程序中的存储访问构建关于变量的冲突图,对分块内存进行存储块分配,优化数据在分块内存的分布.以数据在分块内存的优化分布为基础,指导程序中访存操作在地址生成单元的优化分配,使得编译器生成的代码可以最大程度地挖掘程序中数据访问的并行性.实验表明,基于分块内存的数据分配分布优化为其它优化如地址寄存器的分簇、访存向量化、软件流水等经典优化提供了良好基础,保证了编译器生成的代码可以充分发挥魂芯DSP提供的指令级并行能力.
[Abstract]:In order to improve the efficiency of memory access, we provide several independent memory access pipeline, which can be executed in parallel with the computation pipeline. The memory on the DSP chip is designed with a block memory structure.A plurality of independent address generation units are provided in the core for memory access operations.In view of the structural characteristics of block memory, the compiler constructs a conflict graph about variables for memory access in a program, distributes block memory to block memory, and optimizes the distribution of data in block memory.Based on the optimal distribution of data in block memory, the optimal allocation of memory access operations in address generation units in the program can be used to maximize the parallelism of data access in the compiler generated code.The experimental results show that the data distribution optimization based on block memory provides a good basis for other optimization such as clustering of address registers, memory access vectorization, software income and so on.It ensures that the code generated by the compiler can give full play to the command-level parallelism provided by the Soul Core DSP.
【作者单位】：合肥工业大学计算机与信息学院;中国电子科技集团公司第三十八研究所;中国科学技术大学计算机科学与技术学院;
【基金】：国家“核心电子器件、高端通用芯片及基础软件产品”重大专项(2012ZX01034001-001)资助
【分类号】：TP333

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