无源UHF RFID系统电子标签模拟前端及存储器低功耗分析与研究

发布时间：2018-04-16 09:32

本文选题：无源 + 超高频　；参考：《南开大学》2013年博士论文

【摘要】：RFID(射频识别)技术作为一种非接触式无线自动识别技术,其原理是通过射频信号自动识别对象目标而获取相关数据,识别工作过程中不需要人工干预,被认为是条形码无线的版本。RFID技术作为物联网的重要组成部分,随着智慧城市等新兴生活理念及科技理念的产生,它必将得到迅速的发展。近几年,无线超高频识别系统(UHF RFID)技术正在被迅速的应用,特别是在供应链、真假识别、车辆跟踪、产品跟踪等领域受到广泛关注。同时嵌入式EEPROM系统作为电子标签重要要组成部分也广泛应用于这些领域。本论文重点研究了无源超高频射频识别标签芯片模拟前端及EEPROM存储器的设计。在论文的开始,论述了RFID系统整体架构以及其RFID系统工作的原理,并且对与设计相关的协议标准进行了分析与比较。之后,对无源UHF超高频无线射频识别标签芯片的系统结构进行了设计,对低功耗无源电子标签芯片设计中涉及到的关键技术进行了研究,对设计中的创新点进行了着重的阐述。首先提出一种低功耗的模拟前端解调电路设计。与传统解调电路相比该解调电路结构简单,数据解调速度快。本文提出的电路结构采用简单的开关及反相器电路代替传统电路的滤波及比较器电路,在简化电路结构同时实现数据解调,降低在解调数据过程中的功耗。之后,论文设计了一种存储器控制时序电路,该电路可以完成在读卡器发出指令及数据之后到对存储器擦、写或读操作完成之前对存储器电路的控制。与传统电子标签架构对存储控制原理相比,电路减少了在对存储器操作期间电子标签数字电路部分及模拟前端部分处于工作状态的电路,其最大的作用是降低了电子标签在擦操作与写操作期间的整体功耗。同时该电路结构提高了存储器工作稳定性,实现存储器在工作过程中完全独立于外部电路,防止在对存储器进行操作过程中由于通讯的意外中断而导致对存储器工作进程的影响。另外,论文提出了一种改进的存储阵列结构,它可以克服传统存储结构擦操作与写操作必须分开进行的缺点,实现对存储阵列的擦操作与写操作同时进行,而且降低电路功耗,将每擦写流程的工作时间降低一半,使电子标签工作时间缩短。论文设计了一种适用于无源UHF RFID电子标签芯片的测试及开发平台,对电子标签芯片进行相关功能性验证。该平台可以直接与读卡器通信进行测试,也可以与外部FPGA相连进行测试。论文主要研究放在无源UHF RFID电子标签芯片前端模拟电路的设计和EEPROM存储器电路的系统结构改造。本项目采用的工艺为0.18μm2P4M EEPROM进行流片,采用的通信协议为ISO/IEC18000-6标准。设计电路为具有低功耗高性能特性的UHF RFID电子标签。
[Abstract]:RFID (Radio Frequency Identification) technology as a non-contact wireless automatic identification technology, its principle is to automatically identify the object by radio frequency signals to obtain relevant data, the identification process does not require human intervention,As an important part of the Internet of things, RFID technology is considered to be the wireless version of bar code. With the emergence of new concepts of life and science and technology, such as intelligent city, it will be developed rapidly.In recent years, UHF RFIDs have been applied rapidly, especially in the fields of supply chain, true and false identification, vehicle tracking, product tracking and so on.At the same time, embedded EEPROM system as an important part of electronic label is also widely used in these fields.This paper focuses on the design of passive UHF RFID tag analog front end and EEPROM memory.At the beginning of the thesis, the whole architecture of RFID system and the principle of its RFID system are discussed, and the protocol standards related to the design are analyzed and compared.After that, the system structure of the passive UHF UHF RFID tag chip is designed, the key technologies involved in the design of the low power passive tag chip are studied, and the innovation points in the design are emphasized.A low-power analog front-end demodulation circuit is proposed.Compared with the traditional demodulation circuit, the structure of the demodulation circuit is simple and the speed of data demodulation is fast.In this paper, a simple switch and inverter circuit is used to replace the filter and comparator circuit of the traditional circuit, which can realize the data demodulation while simplifying the circuit structure and reduce the power consumption in the process of demodulation.After that, a memory control sequential circuit is designed, which can control the memory circuit after the reader sends out the instruction and data to the memory erasing, writing or reading operation.Compared with the traditional electronic tag architecture for storage control, the circuit reduces the electronic label digital circuit and analog front-end circuit in working state during the operation of the memory.The biggest effect is to reduce the overall power consumption of the tag during erasure and write operations.At the same time, the circuit structure improves the working stability of the memory and realizes that the memory is completely independent of the external circuit in the working process.To prevent the impact on the memory working process caused by the accidental interruption of communication during the operation of the memory.In addition, an improved memory array structure is proposed, which can overcome the shortcoming that the traditional memory structure erasure operation and write operation must be carried out separately, realize the erasure operation and write operation of the memory array simultaneously, and reduce the power consumption of the circuit.Reduce the working time of each erasure process by half, and shorten the working time of electronic label.A testing and developing platform for passive UHF RFID tag chip is designed in this paper.The platform can directly communicate with the card reader for testing, or can be connected to the external FPGA for testing.This paper mainly focuses on the design of analogue circuit in the front end of passive UHF RFID tag chip and the reconstruction of the system structure of EEPROM memory circuit.The process used in this project is 0.18 渭 m2P4M EEPROM for flow sheet, and the communication protocol is ISO/IEC18000-6 standard.The design circuit is UHF RFID tag with low power consumption and high performance.
【学位授予单位】：南开大学
【学位级别】：博士
【学位授予年份】：2013
【分类号】：TP391.44;TP333

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