基于FPGA自主控制浮点加减乘除控制器设计

发布时间：2018-04-18 14:55

本文选题：FPGA + 浮点数　；参考：《计算机测量与控制》2014年10期

【摘要】：为实现一种能够自主完成浮点数加/减、乘、除运算功能的浮点数算术运算执行控制器,提出了一种基于采用FPGA的并行操作设计硬连接的浮点算术运算控制电路及其时序控制方法,该控制器能够自动选择运算器,调整内部时序脉冲的时钟周期,自主完成操作数的配置并进行浮点数加/减、乘、法运算的功能,运算结果读到系统数据总线;论述了该控制器的电路构成和基本原理,分析操作数配置与运算器的选择,及内部时序脉冲作用下的执行过程,应用Verilog HDL语言实现相关硬件的构建和连接;通过仿真综合测试可知,该控制器的最高频率可达132.426M,从输入端口到输出端口的延时数据为:最小延时是5.367ns,最大延时是18.347ns,耗用的IO输入输出端口占总资源的31.45%;并能够自动选择运算器,自主完成相应的算术运算。
[Abstract]:In order to realize a floating-point arithmetic arithmetic execution controller, which can add / subtract, multiply and divide floating-point number independently,This paper presents a hard-connected floating-point arithmetic arithmetic control circuit based on parallel operation with FPGA and its timing control method. The controller can automatically select the operator and adjust the clock period of the internal timing pulse.The function of floating point addition / subtraction, multiplication, operation, and the result of operation are read to the system data bus, the circuit structure and basic principle of the controller are discussed, and the optograph configuration and the choice of the operator are analyzed.Verilog HDL language is used to realize the construction and connection of related hardware.The maximum frequency of the controller is 132.426M. the delay data from the input port to the output port are as follows: the minimum delay is 5.367ns, the maximum delay is 18.347ns, the IO input and output ports consumed account for 31.45% of the total resources, and the operator can be automatically selected.Autonomous completion of the corresponding arithmetic operation.
【作者单位】：广西科技大学电气与信息工程学院;
【基金】：桂科自(2011GXNSFA018153)
【分类号】：TP332

【参考文献】