面向高性能CPU的锁相环低抖动技术研究

发布时间：2018-04-19 12:03

本文选题：高性能CPU + 锁相环　；参考：《国防科学技术大学》2013年博士论文

【摘要】：半导体工艺进入纳米时代，在工艺的推动下CPU技术取得了长足的进步，特别是高性能CPU的工作主频得到了大幅度的提升，以IBM Power系列为代表的先进微处理器的工作主频已经超过了5GHz。高工作主频对时钟系统的稳定性提出了很高的要求，时钟系统任何微小抖动就可能导致CPU的性能下降或者功能异常。锁相环作为首选的时钟发生器无可取代地成为了几乎所有CPU芯片时钟系统的原点。与工作在其它场合的锁相环不同，高性能CPU内部成分复杂的电源噪声、剧烈波动的芯片温度以及锁相环内部件的电路特性都会影响锁相环的抖动性能，从而成为限制CPU性能的一个重要因素。因此，站在CPU的视角，全面地看待锁相环的抖动问题，研究以面向高性能CPU应用为背景的锁相环低抖动技术成为了高性能CPU研究的先决条件之一。从高性能CPU对锁相环的特性需求出发，本文紧密围绕锁相环的抖动问题，对由CPU内电源噪声、环境温度这类“外在”因素，以及环路内压控振荡器结构这类“内在”因素导致的锁相环抖动问题分别进行了机理分析，并针对性地提出了解决方案。本文的主要创新点可归纳为以下五个方面： 1.从高性能CPU的视角审视锁相环的抖动问题，结合CPU的特点分析产生抖动的外在和内在因素，确立锁相环低抖动设计的目标和着力点。针对为高性能CPU提供高频稳定时钟这一应用目标，本文跳出锁相环环路这一既定框架，从更广阔的视角审视锁相环的抖动问题。以环路内外结合的方式，从CPU的角度分析了高性能CPU固有的电气、温度因素对锁相环抖动特性的影响，提炼出时钟抖动与电源、时钟抖动与偏置、时钟抖动与电路结构之间的内在联系，确定低抖动研究的方向和目标。 2.提出了电流控制模式的低压差稳压器（LDO）模型，并采用提出的八边形网格状大尺寸功率晶体管版图结构，实现了一种内嵌式采用电流控制型LDO锁相环供电电路。针对高性能CPU内部复杂的电源噪声，依据“本地产生，本地使用”的原则，本文提出了内嵌LDO的锁相环供电结构框架，最大限度地降低外界噪声耦合进入锁相环电源网络的可能性。同时，本文还提出了基于电流环路控制技术的流控型LDO结构——CCL-LDO，在CCL-LDO环路中应用电流控制技术，发挥电流信号响应速度快的特点，大幅度地提高了LDO电路的瞬态响应能力，在面对锁相环这类处于振荡状态的负载时能有效稳定供电电压、降低纹波，从“外因”上降低锁相环输出发生抖动的可能性。CCL-LDO分别作用于电荷泵和压控振荡器的实验结果表明，其对电荷泵和压控振荡器相位噪声的抑制可达-40dB～-60dB，能大幅度地降低锁相环输出时钟的抖动。此外，大尺寸功率晶体管也是影响LDO性能的一个重要因素，本文提出了大尺寸功率晶体管的八边形网格状版图实现技术，有效地抑制了大尺寸功率晶体管的衬底偏压累积，确保了大尺寸功率晶体管阈值电压的稳定。 3.针对CPU芯片特点，提出了两种高温度稳定性的带隙基准电路，降低了偏置信号温度漂移对锁相环工作稳定性的影响。针对CPU在不同工作负载下温度波动剧烈的问题，深入地研究了带隙基准电压/电流源电路偏置技术，发现并分析了带隙基准核心电路中由PNP管“发射极-基极”电流通路的分流作用导致的温度漂移现象，，提出了“发射极-基极”电流补偿方案，利用不同材料的温度特性实现了电阻的温度漂移补偿，并在此基础上分别实现了两款高温度稳定性的带隙基准电压/电流源电路。分析表明，基于带隙基准的偏置信号温度稳定性达到1ppm/℃级别，确保了锁相环环路的直流工作状态的稳定。 4.深入分析压控振荡器（VCO）工作过程中的非平衡因素，揭示并分析了压控振荡器的“本征抖动”现象，并针对性地提出了双环互锁/多环前馈自交叉式单端VCO结构。通过对压控振荡器振荡机理的分析，揭示了单端压控振荡器非对称结构导致的“本征抖动”现象，分析了振荡过程中正负半周期内工作电流非平衡这一产生本征抖动的根本机理。针对本征抖动问题，提出了双环互锁压控振荡器结构，并在此基础上进一步地衍生出多环前馈自交叉技术，实现了中心对称的“偶数级单端压控振荡器”，平衡了压控振荡器的工作电流，对“本征抖动”的抑制效果大于80%，并且具有极佳的线性度。 5.针对电源噪声和控制电压噪声导致的VCO抖动，提出并实现了内嵌有源LC滤波器的压控振荡器技术。从VCO的组成结构上看，来自电源和控制电压的噪声均可导致输出抖动，本文深入地分析了这两类噪声的传播方式和机理，提出了在噪声传播路径公共点进行噪声滤波的方法，并结合CPU工艺的特点，提出了内嵌有源LC滤波的压控振荡器技术，有效地衰减了进入环形振荡器的噪声，锁相环的抖动降低超过-30dB。基于上述技术，本文设计了一款基于40nm工艺的低抖动锁相环电路，分析结果表明，对比简单结构的锁相环电路，该锁相环电气原因导致的抖动的均方根值降低了66%，温度因素导致的抖动的均方根值下降了58%。
[Abstract]:The semiconductor technology has entered the nanoscale era. The CPU technology has made great progress in the process of technology, especially the main frequency of the high performance CPU has been greatly improved. The main frequency of the advanced microprocessor, represented by the IBM Power series, has exceeded the 5GHz. high working master frequency to the stability of the clock system. Any tiny jitter in the clock system may lead to CPU performance degradation or function abnormality. Phase locked loop, as the preferred clock generator, becomes the origin of almost all CPU chip clock systems. Unlike the phase locked loops working on other occasions, the complex power noise and volatile core of the high performance CPU inner components are complex. The chip temperature and the circuit characteristics of the components in the phase-locked loop will affect the jitter performance of the PLL, thus becoming an important factor restricting the performance of CPU. Therefore, from the perspective of CPU, the jitter of the PLL is viewed in a comprehensive way, and the low jitter technology based on the high performance CPU application is studied in the high performance CPU research. One of the prerequisites.
Based on the characteristic demand of high performance CPU for phase locked loop, this paper focuses on the jitter of phase-locked loop, and analyzes the mechanism of the phase-locked loop jitter caused by the "internal" factors such as the power noise in the CPU, the ambient temperature, and the internal factors such as the inner loop voltage controlled oscillator structure. The main innovations of this paper can be summed up in the following five aspects:
1. from the perspective of high performance CPU, we examine the jitter of PLL, combine the characteristics of CPU to analyze the external and internal factors of the jitter, and establish the target and focus of the low jitter design of the PLL.
In order to provide high frequency stable clock for high performance CPU, this paper jumps out the established framework of PLL loop to examine the jitter of PLL from a broader perspective. The effect of temperature factors on the jitter characteristics of phase locked loop is analyzed from the angle of CPU and the influence of temperature factors on the jitter characteristics of phase locked loop from the way of combining the loop inside and outside the loop. The relationship between clock jitter and power supply, clock jitter and offset, clock jitter and circuit structure is determined, and the direction and goal of low jitter research are determined.
2. a current control model of low voltage differential voltage regulator (LDO) is proposed, and a new type of LDO PLL power supply circuit with current controlled type is realized by using the proposed eight edge shaped grid like large size power transistor layout structure.
In view of the complex power noise inside the high performance CPU, according to the principle of "local generation and local use", this paper proposes a PLL power supply framework with embedded LDO to minimize the possibility of external noise coupling into the PLL power network. At the same time, the flow control LDO based on current loop control technology is also proposed. Structure - CCL-LDO, the application of current control technology in the CCL-LDO loop, which gives full play to the fast response of the current signal, greatly improves the transient response ability of the LDO circuit. It can effectively stabilize the power supply voltage, reduce the ripple and reduce the output of the PLL from the "external cause" in the face of the phase locked loop such as the oscillating state. The possibility of jitter effect on the experimental results of the charge pump and the voltage controlled oscillator show that the phase noise of the charge pump and the voltage controlled oscillator can be suppressed by -40dB to -60dB, which can greatly reduce the jitter of the output clock of the PLL.
In addition, large size power transistors are also an important factor affecting the performance of LDO. In this paper, a eight edge grid pattern realization technique for large size power transistors is proposed, which effectively inhibits the accumulation of bias voltage of large size power transistors and ensures the stability of the threshold voltage of large size power transistors.
3. according to the characteristics of CPU chip, two kinds of bandgap reference circuits with high temperature stability are proposed, which reduces the effect of bias signal temperature drift on the stability of PLL.
In view of the severe temperature fluctuation of CPU under different working loads, the bias technology of bandgap voltage / current source circuit is deeply studied. The temperature drift caused by the shunt action of the "emitter base" current path of the PNP tube is found and analyzed in the bandgap reference core circuit, and the "emitter base" current is proposed. The compensation scheme is used to compensate the temperature drift of the resistance by using the temperature characteristics of different materials. On this basis, two bandgap voltage / current source circuits with high temperature stability are realized. The analysis shows that the temperature stability of the bias signal based on the bandgap datum reaches the level of 1ppm/ C, which ensures the DC working form of the phase locked loop. The state is stable.
4. the nonequilibrium factors in the working process of the voltage controlled oscillator (VCO) are deeply analyzed, and the "eigenjitter" phenomenon of the VCO is revealed and analyzed, and the double ring interlocking / multi loop feedforward self crossing single end VCO structure is proposed.
By analyzing the oscillation mechanism of the voltage controlled oscillator, the phenomenon of "intrinsic jitter" caused by the asymmetric structure of a single terminal voltage controlled oscillator is revealed. The fundamental mechanism of the eigenjitter in the positive and negative half cycle of the oscillating process is analyzed, and the structure of the double ring interlocked voltage controlled oscillator is proposed. On this basis, the multi loop feed-forward self crossing technique is further derived, which realizes the centrally symmetric "even number single end voltage controlled oscillator", which balances the operating current of the VCO, and the suppression effect of the "eigenjitter" is greater than 80%, and has excellent linearity.
5. aiming at VCO jitter caused by power noise and voltage noise, a voltage controlled oscillator with embedded active LC filter is proposed and implemented.
From the structure of the VCO, the noise from the power supply and the control voltage can cause the output jitter. In this paper, the propagation mode and mechanism of the two kinds of noise are analyzed. The noise filtering method is proposed in the common point of the noise propagation path, and the voltage controlled oscillator with the active LC filter is proposed in combination with the characteristics of the CPU process. It effectively attenuates the noise entering the ring oscillator, and the jitter of the PLL is reduced by more than -30dB.
Based on the above technology, a low jitter PLL circuit based on 40nm technology is designed. The analysis results show that the root mean square value of the jitter of the phase locked loop is reduced by 66%, and the mean square root of the jitter caused by the temperature factor is reduced by 58%..

【学位授予单位】：国防科学技术大学
【学位级别】：博士
【学位授予年份】：2013
【分类号】：TP332;TN911.8

【参考文献】