嵌入式系统中低功耗Cache的重构技术研究

发布时间：2018-04-20 08:39

本文选题：低功耗 + Cache　；参考：《湖南大学》2012年硕士论文

【摘要】：随着集成电路进入深亚微米和纳米级工艺阶段，嵌入式微处理器系统的功耗问题已经成为制约新一代微处理器系统发展最主要的因素之一。Cache技术是基于程序的局部性原理，为缓解主存与处理器的速度不匹配而引入的，是优化计算机系统性能的关键技术。同时，Cache的功耗也占到了整个嵌入式微处理器系统功耗的一半左右。因此，设计高性能、低功耗的Cache结构对提高整个嵌入式系统性能和降低系统功耗有着重大的意义。可重构技术是目前备受关注的一种Cache低功耗技术。它基于资源合理分配原则，使Cache具有可变的配置参数集，并根据应用程序对资源的需求情况配置Cache结构，使Cache资源得到有效的利用。建立在可重构技术之上的自适应Cache重构算法能够动态统计Cache的行为和性能信息并根据这些信息在程序运行时动态地改变Cache的配置，进而在保证性能的前提下，有效地降低Cache功耗。本文针对嵌入式系统环境，提出了两种自适应Cache重构算法。这两种算法都利用状态机在程序运行过程中动态分析程序的局部性特征，根据程序变化，动态配置Cache的容量和相联度。第一种算法是利用程序跳转频率作为程序特征的监测参数，，以此判断重构时机，然后根据Cache访问缺失率情况，运用优化的结构搜索方法在最短时间内找到该段程序最合适的匹配结构。这种算法比第二种算法更容易实现。经实验仿真发现，相比传统固定Cache结构，该方案可以平均降低约39%的功耗。第二种算法改进了第一种算法，摒弃了第一种算法中采用程序跳转率作为衡量程序特征是否变化的参数，加入了程序工作集的思想，通过分析指令工作集签名来判断程序段是否发生了变化，这使程序段的特征变化监测更加精确，有效减少了冗余重构和错失重构的次数。实验仿真发现，相比传统固定Cache结构，该方案可以平均降低约64%的功耗，最大可降低68%。同样地，该算法最大能减小96%的Cache缺失率并能减少3%的应用程序运行时钟周期数。
[Abstract]:As integrated circuits enter deep submicron and nanoscale processes, the power consumption of embedded microprocessor systems has become one of the most important factors restricting the development of new generation microprocessor systems. Cache technology is based on the principle of program locality. In order to mitigate the mismatch between main memory and processor speed, it is a key technology to optimize the performance of computer system. At the same time, the power consumption of Cache accounts for about half of the power consumption of the embedded microprocessor system. Therefore, it is of great significance to design a high performance, low power Cache architecture to improve the performance of the whole embedded system and reduce the power consumption of the system. Reconfigurable technology is a kind of low power Cache technology. Based on the principle of rational resource allocation, Cache has a variable set of configuration parameters, and the Cache structure is configured according to the requirements of the application program, so that the Cache resources can be utilized effectively. The adaptive Cache refactoring algorithm based on reconfigurable technology can dynamically statistics the behavior and performance information of Cache and dynamically change the configuration of Cache while the program is running according to these information. The power consumption of Cache is reduced effectively. In this paper, two adaptive Cache reconstruction algorithms are proposed for embedded system environment. Both algorithms use the state machine to dynamically analyze the local characteristics of the program and dynamically configure the capacity and the degree of association of the Cache according to the program changes. In the first algorithm, the program jump frequency is used as the monitoring parameter of the program feature to judge the time of reconstruction, and then according to the Cache access loss rate, The optimal structure search method is used to find the most suitable matching structure in the shortest time. This algorithm is easier to implement than the second one. The experimental results show that the proposed scheme can reduce the power consumption by about 39% compared with the traditional fixed Cache structure. The second algorithm improved the first algorithm, abandoned the first algorithm to use the program jump rate as a parameter to measure the change of program characteristics, and added the idea of program working set. By analyzing the signature of the working set of instructions to determine whether the program segment has changed or not, it makes the feature change monitoring of the program segment more accurate, and effectively reduces the number of redundant and missed reconfiguration. The experimental results show that compared with the conventional fixed Cache architecture, the proposed scheme can reduce the power consumption by about 64% on average and reduce the maximum power consumption by 68%. Similarly, the algorithm can reduce the Cache deletion rate by 96% and the application clock cycle by 3%.
【学位授予单位】：湖南大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332

【参考文献】