基于MicroBlaze的PCIe协议适应层设计

发布时间：2018-04-21 14:39

本文选题：协议适应层 + MicroBlaze　；参考：《天津大学》2012年硕士论文

【摘要】：在计算机和工业系统中，设备之间经常需要进行高速的数据交换，随着数据传输速率的提高，设备之间进行数据传输存在的最大的问题是数据按照某种协议进行传输后造成时钟不同步，进而导致数据的丢失，当传输速率达到Gbps时这一问题更加严重。解决这一问题的关键技术是在设备间添加一个可以硬件实现的协议适应层。协议适应层（Protocol Adaptation Layers，PAL）是WiGig联盟定义的、在60GHz频段上支持特定数据和显示的协议标准。PAL不仅支持音视频接口，如HDMI和DisplayPort，还支持通用I/O，如USB和PCIe，并且允许这些标准的接口以无线传输的方式直接访问Mac层和物理层。相比于其他通过软件实现的协议，PAL可以在硬件中开发和实现，从而可以最大化的提高性能和降低功耗。从WiGig的定义上看，PAL既支持PCIe接口，也提供对USB3.0接口的支持，，但是目前Xilinx公司所提供的FPGA开发板尚未提供对USB3.0的支持，因此，本文针对PCIe接口的PAL进行了设计和开发。本文基于Xilinx Virtex-6FPGA搭建PCIe接口的PAL硬件平台，PC端驱动将数据通过PCIe接口传输到FPGA上，MicroBlaze软核处理器调用AXI4总线对数据进行接收和处理，处理后的数据经过GTX高速收发器传输到下一级FPGA中。经过规范化CSP语言对整个系统模型的验证和优化后，本文所搭建的PAL平台在Xilinx ML605开发板上进行了测试，PC端传输数据到FPGA上的速度可达6.4Gbps，FPGA之间数据的传输速度可达3.2Gbps。
[Abstract]:In computer and industrial systems, high speed data exchange is often needed between devices. With the increase of data transmission rate, the biggest problem of data transmission between devices is that the data is not synchronized after a certain protocol is transmitted, which leads to the loss of data, which is when the transmission rate reaches Gbps. The problem is even more serious. The key technology to solve this problem is to add a protocol adaptation layer that can be implemented by hardware between devices.
The Protocol Adaptation Layers (PAL) is defined by the WiGig alliance. The protocol standard.PAL that supports specific data and display on the 60GHz band not only supports audio and video interfaces, such as HDMI and DisplayPort, but also supports general I/O, such as USB and PCIe, and allows these standard interfaces to access the layers and objects directly in a wireless transmission. Compared with other protocols implemented by software, PAL can be developed and implemented in hardware, thus maximizing performance and reducing power consumption.
From the definition of WiGig, PAL not only supports the PCIe interface, but also provides support to the USB3.0 interface, but the FPGA development board provided by Xilinx has not yet provided the support for USB3.0. Therefore, this paper has designed and developed the PAL for the PCIe interface. This paper is based on Xilinx Virtex-6FPGA to build the hardware platform of the PCIe interface. The data is transmitted to FPGA through the PCIe interface, and the MicroBlaze soft core processor calls the AXI4 bus to receive and process the data. The processed data is transmitted to the next level FPGA through the GTX high-speed transceiver. After the verification and optimization of the whole system model by the standardized CSP language, the PAL platform built in this paper is developed in Xilinx ML605. The test on board shows that the speed of transmitting data from PC terminal to FPGA can reach 6.4Gbps, and the speed of data transmission between FPGA can reach 3.2Gbps..

【学位授予单位】：天津大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP334.7

【参考文献】