基于程序访存模式的存储系统节能技术研究

发布时间：2018-04-21 14:58

本文选题：节能 + 缓存　；参考：《浙江大学》2013年博士论文

【摘要】：半导体技术的进步和应用对计算能力的需求推动着计算机体系结构的发展。计算机系统计算的数据和指令皆来自于存储系统,存储系统在计算性能中扮演了极其重要的角色。作为对不断提升的计算能力的配合和支持,现有的存储层次系统,无论是片上缓存还是片外内存,其组织结构变得越来越复杂,其容量也变得越来越大。导致的结果是存储层次系统的能耗在整个计算机系统中所占的份额也越来越大。能耗问题会成为目前计算机系统设计中的关键因素。因此如河降低存储层次的功耗,尤其是片上缓存和片外内存的能耗,成为研究者普遍关心的一个重要问题。目前存储系统低功耗研究主要焦点在缓存和内存,因为两者能耗在整个存储层次系统中最显著。当前的内存节能技术为充分发挥器件自带的硬件节能支持,包括内存分块和低功耗状态两种技术,通过软硬件结合的技术节能。另外,新型非易失性存储器由于其静态能耗低、密度大等特点,被考虑作为低功耗存储系统的实现。例如现有的PCM/DRAM混合内存系统就是整合两种器件优点的设计,以及基于STT-RAM的非易失性缓存。上述技术都关注于器件能力的挖掘,而忽视了器件对程序行为的适配,因此不能完美发挥软硬件协同的优势。本文从程序访存行为入手,分析了访存模式的三方面因素：应用程序对内存块的访问行为、应用程序对缓存块的写行为以及应用程序中物理页的写行为。基于这些访存模式,结合现有的存储低功耗技术,本文提出了基于程序访存模式的存储系统节能技术,主要从以下三个方面进行了研究： 1、本文通过追踪程序访问的物理贞的地址,建立了程序数据到内存分块的映射模型；基于该模型,本文抽象出程序执行顺序对于内存块节能的问题,并且采用网络流技术对该问题进行解答；进一步考察了多核上来自不同处理器的程序运行对内存块节能的影响,对该问题进行抽象建模；对于双核系统,本文提出该问题的最优算法解；当其中的处理器数目超过两个时,该问题属于NP难问题,本文提出两个相应的启发式算法。 2、本文研究了程序对缓存的写访问,发现对缓存块的写操作具有集中性；基于该模式,本文提出了选择性的写前读机制,对缓存中的脏字数据进行追踪和标示,利用这些标示信息在缓存块写回操作时只对缓存块中的脏区域触发写前读操作；对于多级STT-RAM缓存写能耗更大的特点,本文研究了数据在多级STT-RAM缓存本地进行写更新以及在SRAM中进行写更新的能耗的差别,提出了伴随写缓存结构和对应的机制,将能耗高的写更新操作迁移到伴随写缓存中,从而达到节能目的。 3、本文研究了程序对物理页的写访问,发现对物理页的两种基本写模式；基于上述写模式,本文提出了具有可变迁移粒度的自适应数据迁移策略,可以识别出当前物理页的写模式,并且采用适合当前物理页的迁移粒度将PCM中的数据迁移至DRAM,减小迁移代价的同时,发挥DRAM写能耗低的特点；在上述的混合内存管理机制下,本文还提出了一种局部刷新的策略,其基本思想是利用迁移模块中的相关信息,对DRAM中的每个数据刷新单元中的数据有效性作标示,从而只对其中的有效数据进行刷新操作,降低数据刷新能耗。最后,本文基于实际的硬件平台PandaBoard和全系统模拟器gem5以及其他的工具如SESC和CACTI,采用实际测量和软件模拟相结合的实验方法,对上述提出的创新和技术进行了实验验证和测试。实验结果表明本文中提出的机制和结构可以比现有的技术进一步降低缓存和内存的写能耗和静态能耗。本文通过对程序访存模式,具体包括应用程序对内存块的访问行为、应用程序对缓存块的写行为以及应用程序中物理页的写行为的研究,结合现有存储器件的节能硬件支持,实现了访存模式指导下对现有存储器件节能潜力的再挖掘,实验结果证实结合软件访存模式的存储节能技术有很好的节能效果。
[Abstract]:The progress and application of semiconductor technology promote the development of computer architecture. The data and instructions of computer systems are derived from the storage system, and the storage system plays an extremely important role in computing performance. As a combination and support for increasing computing power, the existing storage level The system, whether on chip caching or out of chip memory, becomes more and more complex and its capacity becomes larger and larger. The result is that the energy consumption of the storage hierarchy is becoming more and more large in the whole computer system. The energy consumption problem will be the key factor in the design of the current computer system. Reducing the power consumption of storage layer, especially the energy consumption of on-chip cache and off chip memory, has become an important issue that researchers are generally concerned about.
At present, the research of low power consumption in storage system focuses on caching and memory, because the energy consumption is the most significant in the whole storage hierarchy system. The current memory saving technology is to give full play to the hardware energy saving support of the device, including two technologies of memory block and low power consumption, and the technology of combining hardware and software. Non-volatile memory is considered as a low power storage system because of its low energy consumption and high density. For example, the existing PCM/DRAM hybrid memory system is the design of the advantages of the integration of two devices, and the nonvolatile cache based on STT-RAM. The adaptation of program behavior can not give full play to the advantages of software and hardware collaboration.
In this paper, starting with the program visiting behavior, this paper analyzes three factors of the memory visiting mode: the access behavior of the application program to the memory block, the writing behavior of the application program to the cache block and the writing behavior of the physical page in the application. Based on these mode of memory access, combined with the existing storage low power consumption technology, this paper proposes a program based memory mode. The energy saving technology of storage system has been studied from three aspects:
1, by tracing the physical chastity address of the program access, the mapping model of the program data to the memory block is established. Based on this model, this paper abstracts the problem of saving energy of the memory block in the program execution order, and uses the network flow technique to solve the problem. In this paper, the optimal algorithm solution for the problem is proposed in this paper. When the number of processors is more than two, this problem belongs to the NP difficult problem. Two corresponding heuristic algorithms are proposed in this paper.
2, this paper studies the write access to the cache, and finds that the write operation of the cache block is centralized. Based on this mode, this paper proposes a selective pre write reading mechanism to track and mark the dirty word data in the cache, and uses these information to trigger the dirty area in the cache block before writing back to the cache block. Operation; for the higher energy consumption of the multilevel STT-RAM cache, this paper studies the difference in energy consumption between the data in the multi-level STT-RAM cache and the write update in the SRAM, and puts forward the adjoint write cache structure and the corresponding mechanism, and migrates the high energy consumption write update operation to the adjoint write cache to achieve energy saving. Objective.
3, this paper studies the program's write access to physical pages, and finds two basic writing patterns for physical pages. Based on the above write mode, this paper proposes an adaptive data migration strategy with a transition granularity, which can identify the current writing pattern of the physical page, and use the migration granularity of the current physical page to move the data in PCM. At the same time, it is moved to DRAM, reducing the cost of migration and exerting the characteristics of low energy consumption of DRAM. Under the above hybrid memory management mechanism, a local refresh strategy is proposed. The basic idea is to use the related information in the migration module to mark the data validity in each data refresh unit in DRAM, so that only it is used for the data efficiency of each data refresh unit. The effective data is refreshed to reduce the energy consumption of data refresh.
Finally, based on the actual hardware platform PandaBoard and the whole system simulator gem5 and other tools such as SESC and CACTI, the experimental method combined with the actual measurement and software simulation is used to test and test the proposed innovation and technology. The experimental results show that the mechanism and structure proposed in this paper can be compared to the present. Some technologies further reduce the write energy consumption and static energy consumption of cache and memory.
In this paper, through the program access mode, including the access behavior of the application program to the memory block, the writing behavior of the application program to the cache block and the writing behavior of the physical page in the application, and the energy saving hardware support of the existing storage devices, the energy saving potential of the existing memory is realized under the guidance of the memory access mode. The test results confirm that the energy saving technology combined with the software access memory mode has a good energy saving effect.

【学位授予单位】：浙江大学
【学位级别】：博士
【学位授予年份】：2013
【分类号】：TP333

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