专用指令集处理器工程化应用研究

发布时间：2018-04-22 08:34

本文选题：专用指令集处理器 + 互连网络　；参考：《西安电子科技大学》2012年硕士论文

【摘要】：在数字信号处理的应用中，通常采用数字信号处理器(DSP)或者专用集成电路(ASIC)来实现，但是它们都难以同时达到高速处理，，低功耗和灵活应用等要求。而专用指令集处理器(ASIP)既有ASIC的高速性，又包含DSP可编程的特点，能有效权衡两者性能，特别适合在FPGA内以大规模并行处理的方式来实现复杂的应用。本文依托实验室项目，针对ASIP并行体系结构和功能单元（FU）的设计及应用，主要进行了以下四方面工作：第一，针对ASIP并行处理机中各个处理单元之间数据交换的问题，设计了一种基于多端口共享存储器互连网络的紧耦合结构。然后，在此结构上实现了1024点FFT算法，验证了这种结构设计的正确性。第二，针对FFT算法在汇编编程中存在频繁使用同一基本运算的问题，设计了一种专用蝶形运算单元，从而有效减少了指令数目，缩短了执行时间，提高了处理速度。第三，针对微波压缩感知成像算法工程化实现这个项目，提出了一种采用ASIP并行处理结构来实现的解决方案。然后，针对算法在ASIP并行处理机上的可行性进行了研究，得出了一些在ASIP上实现所需要的设计要素。第四，针对H.264压缩项目中二进制算术编码算法硬件的实现提出了一种采用ASIP功能单元嵌入式处理实现的方法。首先，基于ASIP可参量化设计平台设计了一款24位ASIP，并在此ASIP上实现了二进制算术编码。然后，针对二进制算法的特点，对ASIP指令集进行了改进，设计了一种基于桶形移位器的可变长度的移位指令以及实现电路。
[Abstract]:In the application of digital signal processing (DSP) or ASIC, it is difficult to meet the requirements of high speed processing, low power consumption and flexible application at the same time. Special instruction set processor (ASIP) not only has the high speed of ASIC, but also has the programmable characteristics of DSP, so it can effectively balance the performance of both. It is especially suitable for realizing complex applications in FPGA by large-scale parallel processing. This paper, based on the laboratory project, aims at the design and application of ASIP parallel architecture and function unit (FU), mainly carries on the following four aspects of work: Firstly, aiming at the problem of data exchange among processing units in ASIP parallel processor, a tight coupling structure based on multi-port shared memory interconnection network is designed. Then, the 1024 point FFT algorithm is implemented on this structure, which verifies the correctness of the structure design. Secondly, aiming at the problem that FFT algorithm frequently uses the same basic operation in assembly programming, a special butterfly operation unit is designed, which effectively reduces the number of instructions, shortens the execution time and improves the processing speed. Thirdly, aiming at the engineering implementation of microwave compression sensing imaging algorithm, a solution using ASIP parallel processing architecture is proposed. Then, the feasibility of the algorithm in ASIP parallel processing machine is studied, and some design elements for ASIP implementation are obtained. Fourthly, a method of embedded processing based on ASIP function unit is proposed for the hardware implementation of binary arithmetic coding algorithm in H.264 compression project. Firstly, a 24 bit ASIP is designed based on ASIP parameterized design platform, and binary arithmetic coding is implemented on this ASIP. Then, according to the characteristics of binary algorithm, the ASIP instruction set is improved, and a variable length shift instruction based on bucket shifter is designed and implemented.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332

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