一种组合延迟槽和预译码技术的新型分支预测器

发布时间：2018-04-23 23:02

本文选题：分支预测 + SPARC　；参考：《小型微型计算机系统》2015年04期

【摘要】：分支预测是现代微处理器普遍用于提高指令吞吐率的关键技术,随着处理器性能需求的不断增长,分支预测结构越来越复杂,其功耗问题也日益突出.针对SPARC V8架构嵌入式处理器的结构特点和应用需求,设计了一种基于延迟槽的动态分支预测器,以此来提高处理器的预测性能;另外,通过分析动态预测器的几种设计空间,提出采用预译码机制来消除无效访问的电路结构,从而降低预测器的功耗开销.该设计在SMIC 0.13μm工艺下实现,分支预测准确度相比于之前的静态算法提高了21%,动态预测器本身的功耗降低了58%,而整个处理器的面积仅增加1.73%.结果表明,这种组合延迟槽和预译码技术的分支预测思想对SPARC处理器的性能和功耗都达到了很好的优化效果.
[Abstract]:Branch prediction is a key technology widely used in modern microprocessors to improve the throughput of instructions. With the increasing demand for processor performance, the architecture of branch prediction is becoming more and more complex, and the problem of power consumption is becoming more and more prominent. A dynamic branch predictor based on delay slot is designed to improve the performance of embedded processor based on SPARC V8 architecture, and several design spaces of dynamic predictor are analyzed. A predecoding mechanism is proposed to eliminate invalid access to the circuit structure, thus reducing the power consumption of the predictor. The design is implemented in SMIC 0.13 渭 m process. The branch prediction accuracy is 21 times higher than that of the previous static algorithm. The power consumption of the dynamic predictor itself is reduced by 58 and the whole processor area is only increased by 1.73. The results show that the branch prediction idea of the combined delay slot and predecoding technique achieves a good performance and power optimization effect for the SPARC processor.
【作者单位】：西安微电子技术研究所集成电路设计部;
【基金】：国家“八六三”项目(2011AA120204)资助 "十二五"民用航天某预研项目(YY2011-012(D020201))资助
【分类号】：TP332

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