YHFT-Matrix DSP向量存储器的设计及IP软核化

发布时间：2018-04-24 13:57

本文选题：DSP + IP核　；参考：《国防科学技术大学》2013年硕士论文

【摘要】：随着计算机技术和集成电路工艺的发展,微处理器的主频越来越高,中央处理单元(CPU)计算能力的增长远远超过了存储器性能的增加。CPU与存储器之间性能差异的“存储墙”问题已成为制约微处理器整体性能进一步提高的瓶颈。而在面向无线通信、图像处理等流媒体应用的向量处理器中,存储墙的问题尤为严重。如何为向量处理器中的向量处理单元提供更为灵活和高效的向量数据访存方式,发挥向量处理单元的计算能力,扩展向量处理器的应用范围及其在片上系统(System-on-Chip,SoC)上的集成是设计高性能向量处理器、提高其市场竞争力的关键。 YHFT-Matrix是国防科学技术大学自主研发的一款面向软件无线电(Software Defined Radio, SDR)应用的高性能向量数字信号处理器内核；本文针对YHFT-Matrix内核体系结构及其无线通信相关算法的访存特点,对其片上大容量向量存储器(Vector Memory,VM)及其参数化IP (Intellectual Property)设计展开研究,针对向量访存的效率和灵活性面临的问题,提出了基于SIMD结构的向量访存指令集和向量存储器总体方案,设计实现了支持多宽度SIMD向量数据条件访问和非对齐访问的VM,包括VM中的译码、向量地址计算、向量访存仲裁、数据写回对齐等访存流水线功能模块的逻辑结构。在此基础上,根据YHFT-Matrix IP软核的应用多样性设计需求,提取VM的设计参数,实现了SIMD宽度和存储体容量可配置的参数化IP设计,其中VM IP的SIMD宽度N可设计为2、4、8或16四种配置,向量存储体容量设计为16KB或64KB两种配置。最后对VM IP软核进行了模块级、系统级功能验证和逻辑综合。实验结果表明,在各种设计参数配置情况下VM IP功能正确,满足设计要求；在TMSC的45nm工艺下,达到了700MH的工作频率,最大配置下能同时为向量处理单元(VPU)提供717Gbps的向量访存带宽、357Gbps的DMA数据访问带宽和45Gbps的标量访存带宽,很好满足了向量存储器运算部件对数据吞吐率和访存性能的较高要求。
[Abstract]:With the development of computer technology and integrated circuit technology, the main frequency of microprocessor becomes higher and higher. The increase of computing power of central processing unit (CPU) greatly exceeds the increase of memory performance. The problem of "memory wall" which restricts the performance difference between CPU and memory has become a bottleneck restricting the further improvement of the overall performance of microprocessors. In vector processors for streaming media applications such as wireless communication and image processing, the problem of storage wall is especially serious. How to provide a more flexible and efficient way to access and store vector data for vector processing units in vector processors, so as to give full play to the computing power of vector processing units, The application scope of extended vector processor and its integration on on-chip system (System-on-ChipPU SoC) are the key to design high performance vector processor and improve its market competitiveness. YHFT-Matrix is a high-performance vector digital signal processor kernel developed by the University of National Defense Science and Technology, which is oriented to the application of Software Radio Software Defined Radio (SDRs). This paper aims at the memory access characteristics of the YHFT-Matrix kernel architecture and its wireless communication algorithms. This paper studies the design of VMs and their parameterized IP intellectual property. Aiming at the problems of the efficiency and flexibility of vector memory access, a general scheme of vector access instruction set and VRAM based on SIMD structure is proposed. This paper designs and implements the logic structure of VMs which support multi-width SIMD vector data conditional access and unaligned access, including VM decoding, vector address calculation, vector memory access arbitration, data write-back alignment and other memory access pipeline function modules. On this basis, according to the diversity design requirements of YHFT-Matrix IP soft core, the design parameters of VM are extracted, and the parameterized IP design with configurable SIMD width and storage capacity is realized. The SIMD width N of VM IP can be designed as 2 / 4 / 8 or 16 configurations. Vector storage capacity is designed for 16KB or 64KB configurations. Finally, the module level, system level function verification and logic synthesis of VM IP soft core are carried out. The experimental results show that the VM IP functions are correct and meet the design requirements under various design parameter configurations, and the working frequency of 700MH is achieved under the 45nm process of TMSC. Under the maximum configuration, the vector access bandwidth of 717Gbps and the scalar access bandwidth of 45Gbps can be provided to the vector processing unit (VPUU) at 357Gbps at the same time, which meets the higher requirements of the VRAM operation unit for data throughput and memory access performance.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333

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