一种基于BCH码的NAND Flash控制器的研究与设计

发布时间：2018-04-27 07:21

本文选题：NAND + Flash　；参考：《华中科技大学》2013年硕士论文

【摘要】：NAND Flash存储架构和制造工艺的发展在降低NAND Flash存储器成本的同时，也使得NAND Flash存储器产生错误的概率大大提高，可靠性降低，对NANDFlash控制器的纠错能力提出了更高要求。BCH码是由一种能够纠正多个随机性错误的有限域中的线性分组码，本文对一种基于BCH码的NAND Flash控制器进行研究和设计。首先，，本文介绍了NAND Flash存储器的发展历史，NAND Flash产生错位的原理和BCH纠错码的基本知识，给出了NAND Flash控制器的整体架构，分析了BCH纠错码的理论基础，介绍了NAND Flash存储器的存储结构、外部接口和操作时序。其次，根据BCH码的理论基础确定了本文BCH编译码模块的设计参数为(8640,8192,32)，计算出了本文采用的BCH码最小多项式和生成多项式，设计了8位并行的BCH编码器。结合BCH译码器的数据流特点，采用了两级流水线的BCH译码器结构，设计了8位并行的BCH译码器。然后，在分析NAND Flash操作时序的基础上设计了NAND Flash控制器的主控模块。给出了控制器的总体架构和模块划分，详细介绍了控制器的寄存器组，给出了主控逻辑的设计过程，并详细介绍了NAND Flash控制器读数据、写数据、块擦除等操作的实现方法。最后，对BCH编译码模块和NAND Flash控制器进行了功能仿真，分析了仿真结果，并在12.5MHz的时钟频率下对所设计的NAND Flash控制器进行了FPGA验证，仿真验证结果表明所设计的控制器能够对NAND Flash进行正常的读数据、写数据、块擦除等操作，并能在每组1KB数据中不多于32比特错误时进行纠错。
[Abstract]:The development of NAND Flash storage architecture and manufacturing technology not only reduces the cost of NAND Flash memory, but also increases the probability of producing errors in NAND Flash memory and reduces the reliability. The error-correcting ability of NANDFlash controller is proposed that the. BCH code is a linear block code in finite domain which can correct multiple random errors. In this paper, a NAND Flash controller based on BCH code is studied and designed. Firstly, this paper introduces the development history of NAND Flash memory and the basic knowledge of BCH error-correcting code, gives the whole structure of NAND Flash controller, and analyzes the theoretical basis of BCH error-correcting code. The storage structure, external interface and operation timing of NAND Flash memory are introduced. Secondly, according to the theoretical basis of BCH code, the design parameters of the BCH encoding and decoding module are determined to be the minimum polynomial and generating polynomial of the BCH code adopted in this paper, and the 8-bit parallel BCH encoder is designed. According to the data flow characteristics of BCH decoder, a two-stage pipelined BCH decoder structure is adopted, and an 8-bit parallel BCH decoder is designed. Then, the main control module of NAND Flash controller is designed on the basis of analyzing the timing of NAND Flash operation. The overall architecture and module partition of the controller are given, the register set of the controller is introduced in detail, the design process of the main control logic is given, and the implementation method of reading data, writing data and erasing block of the NAND Flash controller is introduced in detail. Finally, the BCH encoding and decoding module and the NAND Flash controller are simulated, the simulation results are analyzed, and the designed NAND Flash controller is verified by FPGA under the clock frequency of 12.5MHz. The simulation results show that the controller can perform normal reading, writing and block erasure to the NAND Flash, and can correct the errors in each 1KB data group with no more than 32 bits.
【学位授予单位】：华中科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333

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