基于TCN协议的MVB及HDLC通信模块硬件系统设计

发布时间：2018-05-03 01:13

本文选题：嵌入式硬件系统 + FPGA　；参考：《华中科技大学》2012年硕士论文

【摘要】：随着第六次火车提速，主要干线开始以时速200千米每小时的高速运行，火车运行控制系统安全性越来越重要，，机车之间的数据通信越来越频繁。计算机技术在机车车辆上的应用越来越多，列车通信网络及主动控制成为高速列车控制中不可或缺的关键技术。随着微电子技术、计算机技术、数字传输技术的飞速发展，自行设计并实现安全稳定列车通信网络设备需求越来越大。本文介绍了基于嵌入式系统的MVB和HDLC通信模块硬件系统的设计，该系统用于实现列车通信网络（TCN）协议规定的MVB总线数据通信和HDLC总线数据通信。该硬件系统平台包含大容量存储器、高性能处理器以及多种常用外围总线接口，以此为硬件开发平台可实现多种总线数据的交互。论文分析火车运行环境，确定硬件系统运行的工作环境温度范围以及抗震性和防雷击设计；对比不同处理器之间差异，选择ARM作为本系统的核心处理器，设计采用FPGA+ARM硬件平台方案；简要说明MVB总线及HDLC总线对硬件接口的需求；论文采用大量的篇幅对系统的总体结构设计、硬件模块设计、总线接口设计以及硬件调试进行详尽的论述。经过大量的分析和设计工作，本文实现MVB总线及HDLC总线单板设计工作。同时，系统通过CAN总线以及RS485总线实现与其他设备进行数据交互。本系统已顺利通过项目验收，系统工作稳定，性能可靠，各项指标都满足要求。
[Abstract]:With the increase of the speed of the sixth train, the main trunk lines begin to run at a high speed of 200 km / h. The safety of the train operation control system is becoming more and more important, and the data communication between locomotives is becoming more and more frequent. The application of computer technology in locomotive and rolling stock is more and more. Train communication network and active control have become the indispensable key technology in high-speed train control. With the rapid development of microelectronic technology, computer technology and digital transmission technology, the demand for designing and implementing safe and stable train communication network equipment is increasing. This paper introduces the design of the hardware system of MVB and HDLC communication module based on embedded system. The system is used to realize the MVB bus data communication and HDLC bus data communication stipulated in the train communication network. The hardware platform consists of large capacity memory, high performance processor and a variety of common peripheral bus interfaces. This hardware development platform can realize the interaction of many kinds of bus data. This paper analyzes the running environment of the train, determines the temperature range of the operating environment of the hardware system, and the design of seismic resistance and lightning protection, compares the differences between different processors, and selects ARM as the core processor of the system. The hardware platform of FPGA ARM is adopted, the requirement of MVB bus and HDLC bus for hardware interface is briefly explained, the overall structure of the system and the hardware module are designed with a large number of pages. Bus interface design and hardware debugging are discussed in detail. After a lot of analysis and design work, this paper realizes the design of MVB bus and HDLC bus single board. At the same time, the system interacts with other devices through CAN bus and RS485 bus. This system has passed the project acceptance smoothly, the system work stably, the performance is reliable, each index all satisfies the request.
【学位授予单位】：华中科技大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TN919.72;TP368.1

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